1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 13 * 14 * @(#)cpu.h 8.4 (Berkeley) 01/05/94 15 */ 16 17 /* 18 * Exported definitions unique to hp300/68k cpu support. 19 */ 20 21 /* 22 * definitions of cpu-dependent requirements 23 * referenced in generic code 24 */ 25 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 26 27 #define cpu_exec(p) /* nothing */ 28 #define cpu_swapin(p) /* nothing */ 29 #define cpu_wait(p) /* nothing */ 30 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 31 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 32 33 /* 34 * Arguments to hardclock and gatherstats encapsulate the previous 35 * machine state in an opaque clockframe. One the hp300, we use 36 * what the hardware pushes on an interrupt (frame format 0). 37 */ 38 struct clockframe { 39 u_short sr; /* sr at time of interrupt */ 40 u_long pc; /* pc at time of interrupt */ 41 u_short vo; /* vector offset (4-word frame) */ 42 }; 43 44 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 45 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 46 #define CLKF_PC(framep) ((framep)->pc) 47 #if 0 48 /* We would like to do it this way... */ 49 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 50 #else 51 /* but until we start using PSL_M, we have to do this instead */ 52 #define CLKF_INTR(framep) (0) /* XXX */ 53 #endif 54 55 56 /* 57 * Preempt the current process if in interrupt from user mode, 58 * or after the current trap/syscall if in system mode. 59 */ 60 #define need_resched() { want_resched++; aston(); } 61 62 /* 63 * Give a profiling tick to the current process when the user profiling 64 * buffer pages are invalid. On the hp300, request an ast to send us 65 * through trap, marking the proc as needing a profiling tick. 66 */ 67 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 68 69 /* 70 * Notify the current process (p) that it has a signal pending, 71 * process as soon as possible. 72 */ 73 #define signotify(p) aston() 74 75 #define aston() (astpending++) 76 77 int astpending; /* need to trap before returning to user mode */ 78 int want_resched; /* resched() was called */ 79 80 81 /* 82 * simulated software interrupt register 83 */ 84 extern unsigned char ssir; 85 86 #define SIR_NET 0x1 87 #define SIR_CLOCK 0x2 88 89 #define siroff(x) ssir &= ~(x) 90 #define setsoftnet() ssir |= SIR_NET 91 #define setsoftclock() ssir |= SIR_CLOCK 92 93 /* 94 * CTL_MACHDEP definitions. 95 */ 96 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 97 #define CPU_MAXID 2 /* number of valid machdep ids */ 98 99 #define CTL_MACHDEP_NAMES { \ 100 { 0, 0 }, \ 101 { "console_device", CTLTYPE_STRUCT }, \ 102 } 103 104 /* 105 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 106 * although some of it could probably be put into generic 68k headers. 107 */ 108 109 /* values for machineid */ 110 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 111 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 112 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 113 #define HP_360 3 /* 25Mhz 68030 */ 114 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 115 #define HP_340 5 /* 16Mhz 68030 */ 116 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 117 #define HP_380 7 /* 25Mhz 68040 */ 118 #define HP_433 8 /* 33Mhz 68040 */ 119 120 /* values for mmutype (assigned for quick testing) */ 121 #define MMU_68040 -2 /* 68040 on-chip MMU */ 122 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 123 #define MMU_HP 0 /* HP proprietary */ 124 #define MMU_68851 1 /* Motorola 68851 */ 125 126 /* values for ectype */ 127 #define EC_PHYS -1 /* external physical address cache */ 128 #define EC_NONE 0 /* no external cache */ 129 #define EC_VIRT 1 /* external virtual address cache */ 130 131 /* values for cpuspeed (not really related to clock speed due to caches) */ 132 #define MHZ_8 1 133 #define MHZ_16 2 134 #define MHZ_25 3 135 #define MHZ_33 4 136 #define MHZ_50 6 137 138 #ifdef KERNEL 139 extern int machineid, mmutype, ectype; 140 extern char *intiobase, *intiolimit; 141 142 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 143 #define enablertclock() 144 145 #endif 146 147 /* physical memory sections */ 148 #define ROMBASE (0x00000000) 149 #define INTIOBASE (0x00400000) 150 #define INTIOTOP (0x00600000) 151 #define EXTIOBASE (0x00600000) 152 #define EXTIOTOP (0x20000000) 153 #define MAXADDR (0xFFFFF000) 154 155 /* 156 * Internal IO space: 157 * 158 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 159 * 160 * Internal IO space is mapped in the kernel from ``intiobase'' to 161 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 162 * conversion between physical and kernel virtual addresses is easy. 163 */ 164 #define ISIIOVA(va) \ 165 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 166 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 167 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 168 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 169 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 170 171 /* 172 * External IO space: 173 * 174 * DIO ranges from select codes 0-63 at physical addresses given by: 175 * 0x600000 + (sc - 32) * 0x10000 176 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 177 * their control space and the remaining areas, [0x200000-0x400000) and 178 * [0x800000-0x1000000), are for additional space required by a card; 179 * e.g. a display framebuffer. 180 * 181 * DIO-II ranges from select codes 132-255 at physical addresses given by: 182 * 0x1000000 + (sc - 132) * 0x400000 183 * The address range of DIO-II space is thus [0x1000000-0x20000000). 184 * 185 * DIO/DIO-II space is too large to map in its entirety, instead devices 186 * are mapped into kernel virtual address space allocated from a range 187 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 188 */ 189 #define DIOBASE (0x600000) 190 #define DIOTOP (0x1000000) 191 #define DIOCSIZE (0x10000) 192 #define DIOIIBASE (0x01000000) 193 #define DIOIITOP (0x20000000) 194 #define DIOIICSIZE (0x00400000) 195 196 /* 197 * HP MMU 198 */ 199 #define MMUBASE IIOPOFF(0x5F4000) 200 #define MMUSSTP 0x0 201 #define MMUUSTP 0x4 202 #define MMUTBINVAL 0x8 203 #define MMUSTAT 0xC 204 #define MMUCMD MMUSTAT 205 206 #define MMU_UMEN 0x0001 /* enable user mapping */ 207 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 208 #define MMU_CEN 0x0004 /* enable data cache */ 209 #define MMU_BERR 0x0008 /* bus error */ 210 #define MMU_IEN 0x0020 /* enable instruction cache */ 211 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 212 #define MMU_WPF 0x2000 /* write protect fault */ 213 #define MMU_PF 0x4000 /* page fault */ 214 #define MMU_PTF 0x8000 /* page table fault */ 215 216 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 217 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 218 219 /* 220 * 68851 and 68030 MMU 221 */ 222 #define PMMU_LVLMASK 0x0007 223 #define PMMU_INV 0x0400 224 #define PMMU_WP 0x0800 225 #define PMMU_ALV 0x1000 226 #define PMMU_SO 0x2000 227 #define PMMU_LV 0x4000 228 #define PMMU_BE 0x8000 229 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 230 231 /* 232 * 68040 MMU 233 */ 234 #define MMU4_RES 0x001 235 #define MMU4_TTR 0x002 236 #define MMU4_WP 0x004 237 #define MMU4_MOD 0x010 238 #define MMU4_CMMASK 0x060 239 #define MMU4_SUP 0x080 240 #define MMU4_U0 0x100 241 #define MMU4_U1 0x200 242 #define MMU4_GLB 0x400 243 #define MMU4_BE 0x800 244 245 /* 680X0 function codes */ 246 #define FC_USERD 1 /* user data space */ 247 #define FC_USERP 2 /* user program space */ 248 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 249 #define FC_SUPERD 5 /* supervisor data space */ 250 #define FC_SUPERP 6 /* supervisor program space */ 251 #define FC_CPU 7 /* CPU space */ 252 253 /* fields in the 68020 cache control register */ 254 #define IC_ENABLE 0x0001 /* enable instruction cache */ 255 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 256 #define IC_CE 0x0004 /* clear instruction cache entry */ 257 #define IC_CLR 0x0008 /* clear entire instruction cache */ 258 259 /* additional fields in the 68030 cache control register */ 260 #define IC_BE 0x0010 /* instruction burst enable */ 261 #define DC_ENABLE 0x0100 /* data cache enable */ 262 #define DC_FREEZE 0x0200 /* data cache freeze */ 263 #define DC_CE 0x0400 /* clear data cache entry */ 264 #define DC_CLR 0x0800 /* clear entire data cache */ 265 #define DC_BE 0x1000 /* data burst enable */ 266 #define DC_WA 0x2000 /* write allocate */ 267 268 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 269 #define CACHE_OFF (DC_CLR|IC_CLR) 270 #define CACHE_CLR (CACHE_ON) 271 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 272 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 273 274 /* 68040 cache control register */ 275 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 276 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 277 278 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 279 #define CACHE4_OFF (0) 280