1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.13 89/06/23$ 13 * 14 * @(#)cpu.h 7.3 (Berkeley) 12/05/90 15 */ 16 17 /* values for machineid */ 18 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 19 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 20 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 21 #define HP_360 3 /* 25Mhz 68030 */ 22 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 23 #define HP_340 5 /* 16Mhz 68030 */ 24 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 25 26 /* values for mmutype (assigned for quick testing) */ 27 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 28 #define MMU_HP 0 /* HP proprietary */ 29 #define MMU_68851 1 /* Motorola 68851 */ 30 31 /* values for ectype */ 32 #define EC_PHYS -1 /* external physical address cache */ 33 #define EC_NONE 0 /* no external cache */ 34 #define EC_VIRT 1 /* external virtual address cache */ 35 36 /* values for cpuspeed (not really related to clock speed due to caches) */ 37 #define MHZ_8 1 38 #define MHZ_16 2 39 #define MHZ_25 3 40 #define MHZ_33 4 41 #define MHZ_50 6 42 43 #ifdef KERNEL 44 extern int machineid, mmutype, ectype; 45 extern unsigned long DIObase; 46 47 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 48 #define enablertclock() 49 50 #endif 51 52 /* physical memory sections */ 53 #define ROMBASE (0x00000000) 54 #define IOBASE (0x00200000) 55 #define IOTOP (0x01000000) 56 #define MAXADDR (0xFFFFF000) 57 58 /* DIO space stuff */ 59 #define INTERNALHPIB (0x00478000) 60 #define EXTIOBASE (0x00600000) 61 #define IOCARDSIZE (0x10000) 62 #define IOMAPSIZE (btoc(IOTOP-IOBASE)) 63 #define IOP(x) ((x) - IOBASE) 64 #define IOV(x) (((x) - IOBASE) + DIObase) 65 #define UNIOV(x) ((x) - DIObase + IOBASE) 66 67 /* DIO II uncached address space */ 68 #define DIOIIBASE (0x01000000) 69 #define DIOIITOP (0x20000000) 70 #define DIOIICSIZE (0x00400000) 71 72 /* base/offsets for longword read/write (for locore.s) */ 73 #define MMUBASE IOP(0x5F4000) 74 #define MMUSSTP 0x0 75 #define MMUUSTP 0x4 76 #define MMUTBINVAL 0x8 77 #define MMUSTAT 0xC 78 #define MMUCMD MMUSTAT 79 80 #define MMU_UMEN 0x0001 /* enable user mapping */ 81 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 82 #define MMU_CEN 0x0004 /* enable data cache */ 83 #define MMU_BERR 0x0008 /* bus error */ 84 #define MMU_IEN 0x0020 /* enable instruction cache */ 85 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 86 #define MMU_WPF 0x2000 /* write protect fault */ 87 #define MMU_PF 0x4000 /* page fault */ 88 #define MMU_PTF 0x8000 /* page table fault */ 89 90 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 91 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 92 93 #define PMMU_LVLMASK 0x0007 94 #define PMMU_INV 0x0400 95 #define PMMU_WP 0x0800 96 #define PMMU_ALV 0x1000 97 #define PMMU_SO 0x2000 98 #define PMMU_LV 0x4000 99 #define PMMU_BE 0x8000 100 101 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 102 103 /* 680X0 function codes */ 104 #define FC_USERD 1 /* user data space */ 105 #define FC_USERP 2 /* user program space */ 106 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 107 #define FC_SUPERD 5 /* supervisor data space */ 108 #define FC_SUPERP 6 /* supervisor program space */ 109 #define FC_CPU 7 /* CPU space */ 110 111 /* fields in the 68020 cache control register */ 112 #define IC_ENABLE 0x0001 /* enable instruction cache */ 113 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 114 #define IC_CE 0x0004 /* clear instruction cache entry */ 115 #define IC_CLR 0x0008 /* clear entire instruction cache */ 116 117 /* additional fields in the 68030 cache control register */ 118 #define IC_BE 0x0010 /* instruction burst enable */ 119 #define DC_ENABLE 0x0100 /* data cache enable */ 120 #define DC_FREEZE 0x0200 /* data cache freeze */ 121 #define DC_CE 0x0400 /* clear data cache entry */ 122 #define DC_CLR 0x0800 /* clear entire data cache */ 123 #define DC_BE 0x1000 /* data burst enable */ 124 #define DC_WA 0x2000 /* write allocate */ 125 126 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 127 #define CACHE_OFF (DC_CLR|IC_CLR) 128 #define CACHE_CLR (CACHE_ON) 129 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 130 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 131