1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.13 89/06/23$ 13 * 14 * @(#)cpu.h 7.4 (Berkeley) 04/20/91 15 */ 16 17 #ifdef notyet 18 #include "../hp300/psl.h" 19 #else 20 #include "machine/psl.h" 21 #endif 22 23 /* 24 * Exported definitions unique to hp300/68k cpu support. 25 */ 26 27 /* 28 * definitions of cpu-dependent requirements 29 * referenced in generic code 30 */ 31 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 32 33 /* 34 * function vs. inline configuration; 35 * these are defined to get generic functions 36 * rather than inline or machine-dependent implementations 37 */ 38 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 39 #undef NEED_FFS /* don't need ffs function */ 40 #undef NEED_BCMP /* don't need bcmp function */ 41 #undef NEED_STRLEN /* don't need strlen function */ 42 43 #define cpu_exec(p) /* nothing */ 44 45 /* 46 * Arguments to hardclock, softclock and gatherstats 47 * encapsulate the previous machine state in an opaque 48 * clockframe; for hp300, use just what the hardware 49 * leaves on the stack. 50 */ 51 typedef struct intrframe { 52 int pc; 53 int ps; 54 } clockframe; 55 56 #define CLKF_USERMODE(framep) USERMODE((framep)->ps) 57 #define CLKF_BASEPRI(framep) BASEPRI((framep)->ps) 58 #define CLKF_PC(framep) ((framep)->pc) 59 60 61 /* 62 * Preempt the current process if in interrupt from user mode, 63 * or after the current trap/syscall if in system mode. 64 */ 65 #define need_resched() { want_resched++; aston(); } 66 67 68 /* 69 * Give a profiling tick to the current process from the softclock 70 * interrupt. On hp300, request an ast to send us through trap(), 71 * marking the proc as needing a profiling tick. 72 */ 73 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 74 75 int want_resched; /* resched() was called */ 76 77 78 /* 79 * simulated software interrupt register 80 */ 81 extern unsigned char ssir; 82 83 #define SIR_NET 0x1 84 #define SIR_CLOCK 0x2 85 86 #define siroff(x) ssir &= ~(x) 87 #define setsoftnet() ssir |= SIR_NET 88 #define setsoftclock() ssir |= SIR_CLOCK 89 90 91 92 /* 93 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 94 * although some of it could probably be put into generic 68k headers. 95 */ 96 97 /* values for machineid */ 98 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 99 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 100 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 101 #define HP_360 3 /* 25Mhz 68030 */ 102 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 103 #define HP_340 5 /* 16Mhz 68030 */ 104 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 105 106 /* values for mmutype (assigned for quick testing) */ 107 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 108 #define MMU_HP 0 /* HP proprietary */ 109 #define MMU_68851 1 /* Motorola 68851 */ 110 111 /* values for ectype */ 112 #define EC_PHYS -1 /* external physical address cache */ 113 #define EC_NONE 0 /* no external cache */ 114 #define EC_VIRT 1 /* external virtual address cache */ 115 116 /* values for cpuspeed (not really related to clock speed due to caches) */ 117 #define MHZ_8 1 118 #define MHZ_16 2 119 #define MHZ_25 3 120 #define MHZ_33 4 121 #define MHZ_50 6 122 123 #ifdef KERNEL 124 extern int machineid, mmutype, ectype; 125 extern unsigned long DIObase; 126 127 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 128 #define enablertclock() 129 130 #endif 131 132 /* physical memory sections */ 133 #define ROMBASE (0x00000000) 134 #define IOBASE (0x00200000) 135 #define IOTOP (0x01000000) 136 #define MAXADDR (0xFFFFF000) 137 138 /* DIO space stuff */ 139 #define INTERNALHPIB (0x00478000) 140 #define EXTIOBASE (0x00600000) 141 #define IOCARDSIZE (0x10000) 142 #define IOMAPSIZE (btoc(IOTOP-IOBASE)) 143 #define IOP(x) ((x) - IOBASE) 144 #define IOV(x) (((x) - IOBASE) + DIObase) 145 #define UNIOV(x) ((x) - DIObase + IOBASE) 146 147 /* DIO II uncached address space */ 148 #define DIOIIBASE (0x01000000) 149 #define DIOIITOP (0x20000000) 150 #define DIOIICSIZE (0x00400000) 151 152 /* base/offsets for longword read/write (for locore.s) */ 153 #define MMUBASE IOP(0x5F4000) 154 #define MMUSSTP 0x0 155 #define MMUUSTP 0x4 156 #define MMUTBINVAL 0x8 157 #define MMUSTAT 0xC 158 #define MMUCMD MMUSTAT 159 160 #define MMU_UMEN 0x0001 /* enable user mapping */ 161 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 162 #define MMU_CEN 0x0004 /* enable data cache */ 163 #define MMU_BERR 0x0008 /* bus error */ 164 #define MMU_IEN 0x0020 /* enable instruction cache */ 165 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 166 #define MMU_WPF 0x2000 /* write protect fault */ 167 #define MMU_PF 0x4000 /* page fault */ 168 #define MMU_PTF 0x8000 /* page table fault */ 169 170 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 171 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 172 173 #define PMMU_LVLMASK 0x0007 174 #define PMMU_INV 0x0400 175 #define PMMU_WP 0x0800 176 #define PMMU_ALV 0x1000 177 #define PMMU_SO 0x2000 178 #define PMMU_LV 0x4000 179 #define PMMU_BE 0x8000 180 181 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 182 183 /* 680X0 function codes */ 184 #define FC_USERD 1 /* user data space */ 185 #define FC_USERP 2 /* user program space */ 186 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 187 #define FC_SUPERD 5 /* supervisor data space */ 188 #define FC_SUPERP 6 /* supervisor program space */ 189 #define FC_CPU 7 /* CPU space */ 190 191 /* fields in the 68020 cache control register */ 192 #define IC_ENABLE 0x0001 /* enable instruction cache */ 193 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 194 #define IC_CE 0x0004 /* clear instruction cache entry */ 195 #define IC_CLR 0x0008 /* clear entire instruction cache */ 196 197 /* additional fields in the 68030 cache control register */ 198 #define IC_BE 0x0010 /* instruction burst enable */ 199 #define DC_ENABLE 0x0100 /* data cache enable */ 200 #define DC_FREEZE 0x0200 /* data cache freeze */ 201 #define DC_CE 0x0400 /* clear data cache entry */ 202 #define DC_CLR 0x0800 /* clear entire data cache */ 203 #define DC_BE 0x1000 /* data burst enable */ 204 #define DC_WA 0x2000 /* write allocate */ 205 206 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 207 #define CACHE_OFF (DC_CLR|IC_CLR) 208 #define CACHE_CLR (CACHE_ON) 209 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 210 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 211