1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 13 * 14 * @(#)cpu.h 7.13 (Berkeley) 12/27/92 15 */ 16 17 /* 18 * Exported definitions unique to hp300/68k cpu support. 19 */ 20 21 /* 22 * definitions of cpu-dependent requirements 23 * referenced in generic code 24 */ 25 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 26 27 #define cpu_exec(p) /* nothing */ 28 #define cpu_wait(p) /* nothing */ 29 #define cpu_setstack(p, ap) \ 30 (p)->p_md.md_regs[SP] = ap 31 32 /* 33 * Arguments to hardclock and gatherstats encapsulate the previous 34 * machine state in an opaque clockframe. One the hp300, we use 35 * what the hardware pushes on an interrupt (frame format 0). 36 */ 37 struct clockframe { 38 u_short sr; /* sr at time of interrupt */ 39 u_long pc; /* pc at time of interrupt */ 40 u_short vo; /* vector offset (4-word frame) */ 41 }; 42 43 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 44 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 45 #define CLKF_PC(framep) ((framep)->pc) 46 #if 0 47 /* We would like to do it this way... */ 48 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 49 #else 50 /* but until we start using PSL_M, we have to do this instead */ 51 #define CLKF_INTR(framep) (0) /* XXX */ 52 #endif 53 54 55 /* 56 * Preempt the current process if in interrupt from user mode, 57 * or after the current trap/syscall if in system mode. 58 */ 59 #define need_resched() { want_resched++; aston(); } 60 61 /* 62 * Give a profiling tick to the current process when the user profiling 63 * buffer pages are invalid. On the hp300, request an ast to send us 64 * through trap, marking the proc as needing a profiling tick. 65 */ 66 #define need_proftick(p) { (p)->p_flag |= SOWEUPC; aston(); } 67 68 /* 69 * Notify the current process (p) that it has a signal pending, 70 * process as soon as possible. 71 */ 72 #define signotify(p) aston() 73 74 #define aston() (astpending++) 75 76 int astpending; /* need to trap before returning to user mode */ 77 int want_resched; /* resched() was called */ 78 79 80 /* 81 * simulated software interrupt register 82 */ 83 extern unsigned char ssir; 84 85 #define SIR_NET 0x1 86 #define SIR_CLOCK 0x2 87 88 #define siroff(x) ssir &= ~(x) 89 #define setsoftnet() ssir |= SIR_NET 90 #define setsoftclock() ssir |= SIR_CLOCK 91 92 93 94 /* 95 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 96 * although some of it could probably be put into generic 68k headers. 97 */ 98 99 /* values for machineid */ 100 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 101 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 102 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 103 #define HP_360 3 /* 25Mhz 68030 */ 104 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 105 #define HP_340 5 /* 16Mhz 68030 */ 106 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 107 #define HP_380 7 /* 25Mhz 68040 */ 108 #define HP_433 8 /* 33Mhz 68040 */ 109 110 /* values for mmutype (assigned for quick testing) */ 111 #define MMU_68040 -2 /* 68040 on-chip MMU */ 112 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 113 #define MMU_HP 0 /* HP proprietary */ 114 #define MMU_68851 1 /* Motorola 68851 */ 115 116 /* values for ectype */ 117 #define EC_PHYS -1 /* external physical address cache */ 118 #define EC_NONE 0 /* no external cache */ 119 #define EC_VIRT 1 /* external virtual address cache */ 120 121 /* values for cpuspeed (not really related to clock speed due to caches) */ 122 #define MHZ_8 1 123 #define MHZ_16 2 124 #define MHZ_25 3 125 #define MHZ_33 4 126 #define MHZ_50 6 127 128 #ifdef KERNEL 129 extern int machineid, mmutype, ectype; 130 extern char *intiobase, *intiolimit; 131 132 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 133 #define enablertclock() 134 135 #endif 136 137 /* physical memory sections */ 138 #define ROMBASE (0x00000000) 139 #define INTIOBASE (0x00400000) 140 #define INTIOTOP (0x00600000) 141 #define EXTIOBASE (0x00600000) 142 #define EXTIOTOP (0x20000000) 143 #define MAXADDR (0xFFFFF000) 144 145 /* 146 * Internal IO space: 147 * 148 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 149 * 150 * Internal IO space is mapped in the kernel from ``intiobase'' to 151 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 152 * conversion between physical and kernel virtual addresses is easy. 153 */ 154 #define ISIIOVA(va) \ 155 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 156 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 157 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 158 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 159 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 160 161 /* 162 * External IO space: 163 * 164 * DIO ranges from select codes 0-63 at physical addresses given by: 165 * 0x600000 + (sc - 32) * 0x10000 166 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 167 * their control space and the remaining areas, [0x200000-0x400000) and 168 * [0x800000-0x1000000), are for additional space required by a card; 169 * e.g. a display framebuffer. 170 * 171 * DIO-II ranges from select codes 132-255 at physical addresses given by: 172 * 0x1000000 + (sc - 132) * 0x400000 173 * The address range of DIO-II space is thus [0x1000000-0x20000000). 174 * 175 * DIO/DIO-II space is too large to map in its entirety, instead devices 176 * are mapped into kernel virtual address space allocated from a range 177 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 178 */ 179 #define DIOBASE (0x600000) 180 #define DIOTOP (0x1000000) 181 #define DIOCSIZE (0x10000) 182 #define DIOIIBASE (0x01000000) 183 #define DIOIITOP (0x20000000) 184 #define DIOIICSIZE (0x00400000) 185 186 /* 187 * HP MMU 188 */ 189 #define MMUBASE IIOPOFF(0x5F4000) 190 #define MMUSSTP 0x0 191 #define MMUUSTP 0x4 192 #define MMUTBINVAL 0x8 193 #define MMUSTAT 0xC 194 #define MMUCMD MMUSTAT 195 196 #define MMU_UMEN 0x0001 /* enable user mapping */ 197 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 198 #define MMU_CEN 0x0004 /* enable data cache */ 199 #define MMU_BERR 0x0008 /* bus error */ 200 #define MMU_IEN 0x0020 /* enable instruction cache */ 201 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 202 #define MMU_WPF 0x2000 /* write protect fault */ 203 #define MMU_PF 0x4000 /* page fault */ 204 #define MMU_PTF 0x8000 /* page table fault */ 205 206 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 207 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 208 209 /* 210 * 68851 and 68030 MMU 211 */ 212 #define PMMU_LVLMASK 0x0007 213 #define PMMU_INV 0x0400 214 #define PMMU_WP 0x0800 215 #define PMMU_ALV 0x1000 216 #define PMMU_SO 0x2000 217 #define PMMU_LV 0x4000 218 #define PMMU_BE 0x8000 219 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 220 221 /* 222 * 68040 MMU 223 */ 224 #define MMU4_RES 0x001 225 #define MMU4_TTR 0x002 226 #define MMU4_WP 0x004 227 #define MMU4_MOD 0x010 228 #define MMU4_CMMASK 0x060 229 #define MMU4_SUP 0x080 230 #define MMU4_U0 0x100 231 #define MMU4_U1 0x200 232 #define MMU4_GLB 0x400 233 #define MMU4_BE 0x800 234 235 /* 680X0 function codes */ 236 #define FC_USERD 1 /* user data space */ 237 #define FC_USERP 2 /* user program space */ 238 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 239 #define FC_SUPERD 5 /* supervisor data space */ 240 #define FC_SUPERP 6 /* supervisor program space */ 241 #define FC_CPU 7 /* CPU space */ 242 243 /* fields in the 68020 cache control register */ 244 #define IC_ENABLE 0x0001 /* enable instruction cache */ 245 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 246 #define IC_CE 0x0004 /* clear instruction cache entry */ 247 #define IC_CLR 0x0008 /* clear entire instruction cache */ 248 249 /* additional fields in the 68030 cache control register */ 250 #define IC_BE 0x0010 /* instruction burst enable */ 251 #define DC_ENABLE 0x0100 /* data cache enable */ 252 #define DC_FREEZE 0x0200 /* data cache freeze */ 253 #define DC_CE 0x0400 /* clear data cache entry */ 254 #define DC_CLR 0x0800 /* clear entire data cache */ 255 #define DC_BE 0x1000 /* data burst enable */ 256 #define DC_WA 0x2000 /* write allocate */ 257 258 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 259 #define CACHE_OFF (DC_CLR|IC_CLR) 260 #define CACHE_CLR (CACHE_ON) 261 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 262 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 263 264 /* 68040 cache control register */ 265 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 266 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 267 268 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 269 #define CACHE4_OFF (0) 270