1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * %sccs.include.redist.c% 11 * 12 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 13 * 14 * @(#)cpu.h 7.10 (Berkeley) 06/05/92 15 */ 16 17 /* 18 * Exported definitions unique to hp300/68k cpu support. 19 */ 20 21 /* 22 * definitions of cpu-dependent requirements 23 * referenced in generic code 24 */ 25 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 26 27 /* 28 * function vs. inline configuration; 29 * these are defined to get generic functions 30 * rather than inline or machine-dependent implementations 31 */ 32 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 33 #undef NEED_FFS /* don't need ffs function */ 34 #undef NEED_BCMP /* don't need bcmp function */ 35 #undef NEED_STRLEN /* don't need strlen function */ 36 37 #define cpu_exec(p) /* nothing */ 38 #define cpu_wait(p) /* nothing */ 39 #define cpu_setstack(p, ap) \ 40 (p)->p_md.md_regs[SP] = ap 41 42 /* 43 * Arguments to hardclock, softclock and gatherstats 44 * encapsulate the previous machine state in an opaque 45 * clockframe; for hp300, use just what the hardware 46 * leaves on the stack. 47 */ 48 typedef struct intrframe { 49 char *pc; 50 int ps; 51 } clockframe; 52 53 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 54 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 55 #define CLKF_PC(framep) ((framep)->pc) 56 57 58 /* 59 * Preempt the current process if in interrupt from user mode, 60 * or after the current trap/syscall if in system mode. 61 */ 62 #define need_resched() { want_resched++; aston(); } 63 64 /* 65 * Give a profiling tick to the current process from the softclock 66 * interrupt. On hp300, request an ast to send us through trap(), 67 * marking the proc as needing a profiling tick. 68 */ 69 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 70 71 /* 72 * Notify the current process (p) that it has a signal pending, 73 * process as soon as possible. 74 */ 75 #define signotify(p) aston() 76 77 #define aston() (astpending++) 78 79 int astpending; /* need to trap before returning to user mode */ 80 int want_resched; /* resched() was called */ 81 82 83 /* 84 * simulated software interrupt register 85 */ 86 extern unsigned char ssir; 87 88 #define SIR_NET 0x1 89 #define SIR_CLOCK 0x2 90 91 #define siroff(x) ssir &= ~(x) 92 #define setsoftnet() ssir |= SIR_NET 93 #define setsoftclock() ssir |= SIR_CLOCK 94 95 96 97 /* 98 * The rest of this should probably be moved to ../hp300/hp300cpu.h, 99 * although some of it could probably be put into generic 68k headers. 100 */ 101 102 /* values for machineid */ 103 #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ 104 #define HP_330 1 /* 16Mhz 68020+68851 MMU */ 105 #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ 106 #define HP_360 3 /* 25Mhz 68030 */ 107 #define HP_370 4 /* 33Mhz 68030+64K external cache */ 108 #define HP_340 5 /* 16Mhz 68030 */ 109 #define HP_375 6 /* 50Mhz 68030+32K external cache */ 110 #define HP_380 7 /* 25Mhz 68040 */ 111 112 /* values for mmutype (assigned for quick testing) */ 113 #define MMU_68040 -2 /* 68040 on-chip MMU */ 114 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 115 #define MMU_HP 0 /* HP proprietary */ 116 #define MMU_68851 1 /* Motorola 68851 */ 117 118 /* values for ectype */ 119 #define EC_PHYS -1 /* external physical address cache */ 120 #define EC_NONE 0 /* no external cache */ 121 #define EC_VIRT 1 /* external virtual address cache */ 122 123 /* values for cpuspeed (not really related to clock speed due to caches) */ 124 #define MHZ_8 1 125 #define MHZ_16 2 126 #define MHZ_25 3 127 #define MHZ_33 4 128 #define MHZ_50 6 129 130 #ifdef KERNEL 131 extern int machineid, mmutype, ectype; 132 extern char *intiobase, *intiolimit; 133 134 /* what is this supposed to do? i.e. how is it different than startrtclock? */ 135 #define enablertclock() 136 137 #endif 138 139 /* physical memory sections */ 140 #define ROMBASE (0x00000000) 141 #define INTIOBASE (0x00400000) 142 #define INTIOTOP (0x00600000) 143 #define EXTIOBASE (0x00600000) 144 #define EXTIOTOP (0x20000000) 145 #define MAXADDR (0xFFFFF000) 146 147 /* 148 * Internal IO space: 149 * 150 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 151 * 152 * Internal IO space is mapped in the kernel from ``intiobase'' to 153 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 154 * conversion between physical and kernel virtual addresses is easy. 155 */ 156 #define ISIIOVA(va) \ 157 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 158 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 159 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 160 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 161 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 162 163 /* 164 * External IO space: 165 * 166 * DIO ranges from select codes 0-63 at physical addresses given by: 167 * 0x600000 + (sc - 32) * 0x10000 168 * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for 169 * their control space and the remaining areas, [0x200000-0x400000) and 170 * [0x800000-0x1000000), are for additional space required by a card; 171 * e.g. a display framebuffer. 172 * 173 * DIO-II ranges from select codes 132-255 at physical addresses given by: 174 * 0x1000000 + (sc - 132) * 0x400000 175 * The address range of DIO-II space is thus [0x1000000-0x20000000). 176 * 177 * DIO/DIO-II space is too large to map in its entirety, instead devices 178 * are mapped into kernel virtual address space allocated from a range 179 * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. 180 */ 181 #define DIOBASE (0x600000) 182 #define DIOTOP (0x1000000) 183 #define DIOCSIZE (0x10000) 184 #define DIOIIBASE (0x01000000) 185 #define DIOIITOP (0x20000000) 186 #define DIOIICSIZE (0x00400000) 187 188 /* 189 * HP MMU 190 */ 191 #define MMUBASE IIOPOFF(0x5F4000) 192 #define MMUSSTP 0x0 193 #define MMUUSTP 0x4 194 #define MMUTBINVAL 0x8 195 #define MMUSTAT 0xC 196 #define MMUCMD MMUSTAT 197 198 #define MMU_UMEN 0x0001 /* enable user mapping */ 199 #define MMU_SMEN 0x0002 /* enable supervisor mapping */ 200 #define MMU_CEN 0x0004 /* enable data cache */ 201 #define MMU_BERR 0x0008 /* bus error */ 202 #define MMU_IEN 0x0020 /* enable instruction cache */ 203 #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ 204 #define MMU_WPF 0x2000 /* write protect fault */ 205 #define MMU_PF 0x4000 /* page fault */ 206 #define MMU_PTF 0x8000 /* page table fault */ 207 208 #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) 209 #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) 210 211 /* 212 * 68851 and 68030 MMU 213 */ 214 #define PMMU_LVLMASK 0x0007 215 #define PMMU_INV 0x0400 216 #define PMMU_WP 0x0800 217 #define PMMU_ALV 0x1000 218 #define PMMU_SO 0x2000 219 #define PMMU_LV 0x4000 220 #define PMMU_BE 0x8000 221 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 222 223 /* 224 * 68040 MMU 225 */ 226 #define MMU4_RES 0x001 227 #define MMU4_TTR 0x002 228 #define MMU4_WP 0x004 229 #define MMU4_MOD 0x010 230 #define MMU4_CMMASK 0x060 231 #define MMU4_SUP 0x080 232 #define MMU4_U0 0x100 233 #define MMU4_U1 0x200 234 #define MMU4_GLB 0x400 235 #define MMU4_BE 0x800 236 237 /* 680X0 function codes */ 238 #define FC_USERD 1 /* user data space */ 239 #define FC_USERP 2 /* user program space */ 240 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 241 #define FC_SUPERD 5 /* supervisor data space */ 242 #define FC_SUPERP 6 /* supervisor program space */ 243 #define FC_CPU 7 /* CPU space */ 244 245 /* fields in the 68020 cache control register */ 246 #define IC_ENABLE 0x0001 /* enable instruction cache */ 247 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 248 #define IC_CE 0x0004 /* clear instruction cache entry */ 249 #define IC_CLR 0x0008 /* clear entire instruction cache */ 250 251 /* additional fields in the 68030 cache control register */ 252 #define IC_BE 0x0010 /* instruction burst enable */ 253 #define DC_ENABLE 0x0100 /* data cache enable */ 254 #define DC_FREEZE 0x0200 /* data cache freeze */ 255 #define DC_CE 0x0400 /* clear data cache entry */ 256 #define DC_CLR 0x0800 /* clear entire data cache */ 257 #define DC_BE 0x1000 /* data burst enable */ 258 #define DC_WA 0x2000 /* write allocate */ 259 260 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 261 #define CACHE_OFF (DC_CLR|IC_CLR) 262 #define CACHE_CLR (CACHE_ON) 263 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 264 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 265 266 /* 68040 cache control register */ 267 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 268 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 269 270 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 271 #define CACHE4_OFF (0) 272