1b2e158e7Swilliam /*- 2*2dc74e6cSbostic * Copyright (c) 1991, 1993 3*2dc74e6cSbostic * The Regents of the University of California. All rights reserved. 4b2e158e7Swilliam * 5b2e158e7Swilliam * %sccs.include.redist.c% 6b2e158e7Swilliam * 7*2dc74e6cSbostic * @(#)comreg.h 8.1 (Berkeley) 06/11/93 8b2e158e7Swilliam */ 9b2e158e7Swilliam 10b2e158e7Swilliam 11b2e158e7Swilliam /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 12b2e158e7Swilliam #define COMBRD(x) (1843200 / (16*(x))) 13b2e158e7Swilliam 14b2e158e7Swilliam /* interrupt enable register */ 15b2e158e7Swilliam #define IER_ERXRDY 0x1 16b2e158e7Swilliam #define IER_ETXRDY 0x2 17b2e158e7Swilliam #define IER_ERLS 0x4 18b2e158e7Swilliam #define IER_EMSC 0x8 19b2e158e7Swilliam 20b2e158e7Swilliam /* interrupt identification register */ 218c69e3efSwilliam #define IIR_IMASK 0xf 228c69e3efSwilliam #define IIR_RXTOUT 0xc 238c69e3efSwilliam #define IIR_RLS 0x6 248c69e3efSwilliam #define IIR_RXRDY 0x4 258c69e3efSwilliam #define IIR_TXRDY 0x2 26b2e158e7Swilliam #define IIR_NOPEND 0x1 278c69e3efSwilliam #define IIR_MLSC 0x0 288c69e3efSwilliam #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 298c69e3efSwilliam 308c69e3efSwilliam /* fifo control register */ 318c69e3efSwilliam #define FIFO_ENABLE 0x01 328c69e3efSwilliam #define FIFO_RCV_RST 0x02 338c69e3efSwilliam #define FIFO_XMT_RST 0x04 348c69e3efSwilliam #define FIFO_DMA_MODE 0x08 358c69e3efSwilliam #define FIFO_TRIGGER_1 0x00 368c69e3efSwilliam #define FIFO_TRIGGER_4 0x40 378c69e3efSwilliam #define FIFO_TRIGGER_8 0x80 388c69e3efSwilliam #define FIFO_TRIGGER_14 0xc0 39b2e158e7Swilliam 40b2e158e7Swilliam /* character format control register */ 41b2e158e7Swilliam #define CFCR_DLAB 0x80 42b2e158e7Swilliam #define CFCR_SBREAK 0x40 43b2e158e7Swilliam #define CFCR_PZERO 0x30 44b2e158e7Swilliam #define CFCR_PONE 0x20 45b2e158e7Swilliam #define CFCR_PEVEN 0x10 46b2e158e7Swilliam #define CFCR_PODD 0x00 47b2e158e7Swilliam #define CFCR_PENAB 0x08 48b2e158e7Swilliam #define CFCR_STOPB 0x04 49b2e158e7Swilliam #define CFCR_8BITS 0x03 50b2e158e7Swilliam #define CFCR_7BITS 0x02 51b2e158e7Swilliam #define CFCR_6BITS 0x01 52b2e158e7Swilliam #define CFCR_5BITS 0x00 53b2e158e7Swilliam 54b2e158e7Swilliam /* modem control register */ 55b2e158e7Swilliam #define MCR_LOOPBACK 0x10 56b2e158e7Swilliam #define MCR_IENABLE 0x08 57b2e158e7Swilliam #define MCR_DRS 0x04 58b2e158e7Swilliam #define MCR_RTS 0x02 59b2e158e7Swilliam #define MCR_DTR 0x01 60b2e158e7Swilliam 61b2e158e7Swilliam /* line status register */ 628c69e3efSwilliam #define LSR_RCV_FIFO 0x80 63b2e158e7Swilliam #define LSR_TSRE 0x40 64b2e158e7Swilliam #define LSR_TXRDY 0x20 65b2e158e7Swilliam #define LSR_BI 0x10 66b2e158e7Swilliam #define LSR_FE 0x08 67b2e158e7Swilliam #define LSR_PE 0x04 68b2e158e7Swilliam #define LSR_OE 0x02 69b2e158e7Swilliam #define LSR_RXRDY 0x01 708c69e3efSwilliam #define LSR_RCV_MASK 0x1f 71b2e158e7Swilliam 72b2e158e7Swilliam /* modem status register */ 73b2e158e7Swilliam #define MSR_DCD 0x80 74b2e158e7Swilliam #define MSR_RI 0x40 75b2e158e7Swilliam #define MSR_DSR 0x20 76b2e158e7Swilliam #define MSR_CTS 0x10 77b2e158e7Swilliam #define MSR_DDCD 0x08 78b2e158e7Swilliam #define MSR_TERI 0x04 79b2e158e7Swilliam #define MSR_DDSR 0x02 80b2e158e7Swilliam #define MSR_DCTS 0x01 81b2e158e7Swilliam 828c69e3efSwilliam /* 838c69e3efSwilliam * WARNING: Serial console is assumed to be at COM1 address 848c69e3efSwilliam * and CONUNIT must be 0. 858c69e3efSwilliam */ 868c69e3efSwilliam #define CONADDR (0x3f8) 878c69e3efSwilliam #define CONUNIT (0) 88