1 /*- 2 * Copyright (c) 1982, 1986, 1990, 1991 The Regents of the University of 3 * California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the University of Utah and William Jolitz. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)comreg.h 7.1 (Berkeley) 04/03/91 11 */ 12 13 14 /* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) */ 15 #define COMBRD(x) (1843200 / (16*(x))) 16 17 /* interrupt enable register */ 18 #define IER_ERXRDY 0x1 19 #define IER_ETXRDY 0x2 20 #define IER_ERLS 0x4 21 #define IER_EMSC 0x8 22 23 /* interrupt identification register */ 24 #define IIR_NOPEND 0x1 25 #define IIR_IMASK 0x6 26 #define IIR_RLS 6 27 #define IIR_RXRDY 4 28 #define IIR_TXRDY 2 29 #define IIR_MLSC 0 30 31 /* character format control register */ 32 #define CFCR_DLAB 0x80 33 #define CFCR_SBREAK 0x40 34 #define CFCR_PZERO 0x30 35 #define CFCR_PONE 0x20 36 #define CFCR_PEVEN 0x10 37 #define CFCR_PODD 0x00 38 #define CFCR_PENAB 0x08 39 #define CFCR_STOPB 0x04 40 #define CFCR_8BITS 0x03 41 #define CFCR_7BITS 0x02 42 #define CFCR_6BITS 0x01 43 #define CFCR_5BITS 0x00 44 45 /* modem control register */ 46 #define MCR_LOOPBACK 0x10 47 #define MCR_IENABLE 0x08 48 #define MCR_DRS 0x04 49 #define MCR_RTS 0x02 50 #define MCR_DTR 0x01 51 52 /* line status register */ 53 #define LSR_TSRE 0x40 54 #define LSR_TXRDY 0x20 55 #define LSR_BI 0x10 56 #define LSR_FE 0x08 57 #define LSR_PE 0x04 58 #define LSR_OE 0x02 59 #define LSR_RXRDY 0x01 60 61 /* modem status register */ 62 #define MSR_DCD 0x80 63 #define MSR_RI 0x40 64 #define MSR_DSR 0x20 65 #define MSR_CTS 0x10 66 #define MSR_DDCD 0x08 67 #define MSR_TERI 0x04 68 #define MSR_DDSR 0x02 69 #define MSR_DCTS 0x01 70 71