1 /*- 2 * Copyright (c) 1991, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)ds8390.h 8.1 (Berkeley) 06/11/93 8 */ 9 10 /* 11 * Nominal Semidestructor DS8390 Ethernet Chip 12 * Register and bit definitions 13 */ 14 15 /* 16 * Page register offset values 17 */ 18 #define ds_cmd 0x00 /* Command register: */ 19 #define DSCM_STOP 0x01 /* Stop controller */ 20 #define DSCM_START 0x02 /* Start controller */ 21 #define DSCM_TRANS 0x04 /* Transmit packet */ 22 #define DSCM_RREAD 0x08 /* Remote read */ 23 #define DSCM_RWRITE 0x10 /* Remote write */ 24 #define DSCM_NODMA 0x20 /* No Remote DMA present */ 25 #define DSCM_PG0 0x00 /* Select Page 0 */ 26 #define DSCM_PG1 0x40 /* Select Page 1 */ 27 #define DSCM_PG2 0x80 /* Select Page 2? */ 28 29 #define ds0_pstart 0x01 /* Page Start register */ 30 #define ds0_pstop 0x02 /* Page Stop register */ 31 #define ds0_bnry 0x03 /* Boundary Pointer */ 32 33 #define ds0_tsr 0x04 /* Transmit Status (read-only) */ 34 #define DSTS_PTX 0x01 /* Successful packet transmit */ 35 #define DSTS_COLL 0x04 /* Packet transmit w/ collision*/ 36 #define DSTS_COLL16 0x04 /* Packet had >16 collisions & fail */ 37 #define DSTS_UND 0x20 /* FIFO Underrun on transmission*/ 38 39 #define ds0_tpsr ds0_tsr /* Transmit Page (write-only) */ 40 #define ds0_tbcr0 0x05 /* Transmit Byte count, low WO */ 41 #define ds0_tbcr1 0x06 /* Transmit Byte count, high WO */ 42 43 #define ds0_isr 0x07 /* Interrupt status register */ 44 #define DSIS_RX 0x01 /* Successful packet reception */ 45 #define DSIS_TX 0x02 /* Successful packet transmission */ 46 #define DSIS_RXE 0x04 /* Packet reception w/error */ 47 #define DSIS_TXE 0x08 /* Packet transmission w/error*/ 48 #define DSIS_ROVRN 0x10 /* Receiver overrun in the ring*/ 49 #define DSIS_CTRS 0x20 /* Diagnostic counters need attn */ 50 #define DSIS_RDC 0x40 /* Remote DMA Complete */ 51 #define DSIS_RESET 0x80 /* Reset Complete */ 52 53 #define ds0_rsar0 0x08 /* Remote start address low WO */ 54 #define ds0_rsar1 0x09 /* Remote start address high WO */ 55 #define ds0_rbcr0 0x0A /* Remote byte count low WO */ 56 #define ds0_rbcr1 0x0B /* Remote byte count high WO */ 57 58 #define ds0_rsr 0x0C /* Receive status RO */ 59 #define DSRS_RPC 0x01 /* Received Packet Complete */ 60 61 #define ds0_rcr ds0_rsr /* Receive configuration WO */ 62 #define DSRC_SEP 0x01 /* Save error packets */ 63 #define DSRC_AR 0x02 /* Accept Runt packets */ 64 #define DSRC_AB 0x04 /* Accept Broadcast packets */ 65 #define DSRC_AM 0x08 /* Accept Multicast packets */ 66 #define DSRC_PRO 0x10 /* Promiscuous physical */ 67 #define DSRC_MON 0x20 /* Monitor mode */ 68 69 #define ds0_tcr 0x0D /* Transmit configuration WO */ 70 #define DSTC_CRC 0x01 /* Inhibit CRC */ 71 #define DSTC_LB0 0x02 /* Encoded Loopback Control */ 72 #define DSTC_LB1 0x04 /* Encoded Loopback Control */ 73 #define DSTC_ATD 0x08 /* Auto Transmit Disable */ 74 #define DSTC_OFST 0x10 /* Collision Offset Enable */ 75 76 #define ds0_rcvalctr ds0_tcr /* Receive alignment err ctr RO */ 77 78 #define ds0_dcr 0x0E /* Data configuration WO */ 79 #define DSDC_WTS 0x01 /* Word Transfer Select */ 80 #define DSDC_BOS 0x02 /* Byte Order Select */ 81 #define DSDC_LAS 0x04 /* Long Address Select */ 82 #define DSDC_BMS 0x08 /* Burst Mode Select */ 83 #define DSDC_AR 0x10 /* Autoinitialize Remote */ 84 #define DSDC_FT0 0x20 /* Fifo Threshold Select */ 85 #define DSDC_FT1 0x40 /* Fifo Threshold Select */ 86 87 #define ds0_rcvcrcctr ds0_dcr /* Receive CRC error counter RO */ 88 89 #define ds0_imr 0x0F /* Interrupt mask register WO */ 90 #define DSIM_PRXE 0x01 /* Packet received enable */ 91 #define DSIM_PTXE 0x02 /* Packet transmitted enable */ 92 #define DSIM_RXEE 0x04 /* Receive error enable */ 93 #define DSIM_TXEE 0x08 /* Transmit error enable */ 94 #define DSIM_OVWE 0x10 /* Overwrite warning enable */ 95 #define DSIM_CNTE 0x20 /* Counter overflow enable */ 96 #define DSIM_RDCE 0x40 /* Dma complete enable */ 97 98 #define ds0_rcvfrmctr ds0_imr /* Receive Frame error cntr RO */ 99 100 101 #define ds1_par0 ds0_pstart /* Physical address register 0 */ 102 /* Physical address registers 1-4 */ 103 #define ds1_par5 ds0_tbcr1 /* Physical address register 5 */ 104 #define ds1_curr ds0_isr /* Current page (receive unit) */ 105 #define ds1_mar0 ds0_rsar0 /* Multicast address register 0 */ 106 /* Multicast address registers 1-6 */ 107 #define ds1_mar7 ds0_imr /* Multicast address register 7 */ 108 #define ds1_curr ds0_isr /* Current page (receive unit) */ 109 110 #define DS_PGSIZE 256 /* Size of RAM pages in bytes */ 111 112 /* 113 * Packet receive header, 1 per each buffer page used in receive packet 114 */ 115 struct prhdr { 116 u_char pr_status; /* is this a good packet, same as ds0_rsr */ 117 u_char pr_nxtpg; /* next page of packet or next packet */ 118 u_char pr_sz0; 119 u_char pr_sz1; 120 }; 121