1 /*- 2 * Copyright (c) 1990, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)icu.h 8.1 (Berkeley) 06/11/93 11 */ 12 13 #ifndef __ICU__ 14 #define __ICU__ 15 16 #ifndef LOCORE 17 18 /* 19 * Interrupt "level" mechanism variables, masks, and macros 20 */ 21 extern unsigned short imen; /* interrupt mask enable */ 22 extern unsigned short cpl; /* current priority level mask */ 23 24 extern unsigned short highmask; /* group of interrupts masked with splhigh() */ 25 extern unsigned short ttymask; /* group of interrupts masked with spltty() */ 26 extern unsigned short biomask; /* group of interrupts masked with splbio() */ 27 extern unsigned short netmask; /* group of interrupts masked with splimp() */ 28 29 #define INTREN(s) imen &= ~(s) 30 #define INTRDIS(s) imen |= (s) 31 #define INTRMASK(msk,s) msk |= (s) 32 33 #else 34 35 /* 36 * Macro's for interrupt level priority masks (used in interrupt vector entry) 37 */ 38 39 /* Mask a group of interrupts atomically */ 40 #define INTR_HEAD(unit,mask,offst) \ 41 pushl $ offst ; \ 42 pushl $ T_ASTFLT ; \ 43 pushal ; \ 44 movb $0x20,%al ; \ 45 46 #define INTR_TAIL(unit,mask,offst) \ 47 outb %al,$ IO_ICU1 ; \ 48 pushl %ds ; \ 49 pushl %es ; \ 50 movw $0x10, %ax ; \ 51 movw %ax, %ds ; \ 52 movw %ax,%es ; \ 53 incl _cnt+V_INTR ; \ 54 incl _isa_intr + offst * 4 ; \ 55 movzwl _cpl,%eax ; \ 56 pushl %eax ; \ 57 pushl $ unit ; \ 58 orw mask ,%ax ; \ 59 movw %ax,_cpl ; \ 60 orw _imen,%ax ; \ 61 outb %al,$ IO_ICU1+1 ; \ 62 movb %ah,%al ; \ 63 outb %al,$ IO_ICU2+1 ; \ 64 sti ; 65 66 #define INTR1(unit,mask,offst) \ 67 INTR_HEAD(unit,mask,offst) \ 68 INTR_TAIL(unit,mask,offst) 69 70 #define INTR2(unit,mask,offst) \ 71 INTR_HEAD(unit,mask,offst) \ 72 outb %al,$ IO_ICU2 ; \ 73 INTR_TAIL(unit,mask,offst) 74 75 76 77 /* Interrupt vector exit macros */ 78 79 /* First eight interrupts (ICU1) */ 80 #define INTREXIT1 \ 81 jmp doreti 82 83 /* Second eight interrupts (ICU2) */ 84 #define INTREXIT2 \ 85 jmp doreti 86 87 #endif 88 89 /* 90 * Interrupt enable bits -- in order of priority 91 */ 92 #define IRQ0 0x0001 /* highest priority - timer */ 93 #define IRQ1 0x0002 94 #define IRQ_SLAVE 0x0004 95 #define IRQ8 0x0100 96 #define IRQ9 0x0200 97 #define IRQ2 IRQ9 98 #define IRQ10 0x0400 99 #define IRQ11 0x0800 100 #define IRQ12 0x1000 101 #define IRQ13 0x2000 102 #define IRQ14 0x4000 103 #define IRQ15 0x8000 104 #define IRQ3 0x0008 105 #define IRQ4 0x0010 106 #define IRQ5 0x0020 107 #define IRQ6 0x0040 108 #define IRQ7 0x0080 /* lowest - parallel printer */ 109 110 /* 111 * Interrupt Control offset into Interrupt descriptor table (IDT) 112 */ 113 #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ 114 #define ICU_LEN 16 /* 32-47 are ISA interrupts */ 115 116 #endif __ICU__ 117