1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)icu.h 5.6 (Berkeley) 05/09/91 11 */ 12 13 /* 14 * AT/386 Interrupt Control constants 15 * W. Jolitz 8/89 16 */ 17 18 #ifndef __ICU__ 19 #define __ICU__ 20 21 #ifndef LOCORE 22 23 /* 24 * Interrupt "level" mechanism variables, masks, and macros 25 */ 26 extern unsigned short imen; /* interrupt mask enable */ 27 extern unsigned short cpl; /* current priority level mask */ 28 29 extern unsigned short highmask; /* group of interrupts masked with splhigh() */ 30 extern unsigned short ttymask; /* group of interrupts masked with spltty() */ 31 extern unsigned short biomask; /* group of interrupts masked with splbio() */ 32 extern unsigned short netmask; /* group of interrupts masked with splimp() */ 33 34 #define INTREN(s) imen &= ~(s) 35 #define INTRDIS(s) imen |= (s) 36 #define INTRMASK(msk,s) msk |= (s) 37 38 #else 39 40 /* 41 * Macro's for interrupt level priority masks (used in interrupt vector entry) 42 */ 43 44 /* Mask a group of interrupts atomically */ 45 #define INTR(unit,mask,offst) \ 46 pushl $0 ; \ 47 pushl $ T_ASTFLT ; \ 48 pushal ; \ 49 push %ds ; \ 50 push %es ; \ 51 movw $0x10, %ax ; \ 52 movw %ax, %ds ; \ 53 movw %ax,%es ; \ 54 incl _cnt+V_INTR ; \ 55 incl _isa_intr + offst * 4 ; \ 56 movzwl _cpl,%eax ; \ 57 pushl %eax ; \ 58 pushl $ unit ; \ 59 orw mask ,%ax ; \ 60 movw %ax,_cpl ; \ 61 orw _imen,%ax ; \ 62 NOP ; \ 63 outb %al,$ IO_ICU1+1 ; \ 64 NOP ; \ 65 movb %ah,%al ; \ 66 outb %al,$ IO_ICU2+1 ; \ 67 NOP ; \ 68 inb $0x84,%al ; \ 69 sti 70 71 /* Interrupt vector exit macros */ 72 73 /* First eight interrupts (ICU1) */ 74 #define INTREXIT1 \ 75 movb $0x20,%al ; \ 76 outb %al,$ IO_ICU1 ; \ 77 jmp doreti 78 79 /* Second eight interrupts (ICU2) */ 80 #define INTREXIT2 \ 81 movb $0x20,%al ; \ 82 outb %al,$ IO_ICU1 ; \ 83 outb %al,$ IO_ICU2 ; \ 84 jmp doreti 85 86 #endif 87 88 /* 89 * Interrupt enable bits -- in order of priority 90 */ 91 #define IRQ0 0x0001 /* highest priority - timer */ 92 #define IRQ1 0x0002 93 #define IRQ_SLAVE 0x0004 94 #define IRQ8 0x0100 95 #define IRQ9 0x0200 96 #define IRQ2 IRQ9 97 #define IRQ10 0x0400 98 #define IRQ11 0x0800 99 #define IRQ12 0x1000 100 #define IRQ13 0x2000 101 #define IRQ14 0x4000 102 #define IRQ15 0x8000 103 #define IRQ3 0x0008 104 #define IRQ4 0x0010 105 #define IRQ5 0x0020 106 #define IRQ6 0x0040 107 #define IRQ7 0x0080 /* lowest - parallel printer */ 108 109 /* 110 * Interrupt Control offset into Interrupt descriptor table (IDT) 111 */ 112 #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ 113 #define ICU_LEN 16 /* 32-47 are ISA interrupts */ 114 115 #endif __ICU__ 116