1 /*- 2 * Copyright (c) 1991, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Tim L. Tucker. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_wereg.h 8.1 (Berkeley) 06/11/93 11 */ 12 13 /* 14 * Western Digital 8003 ethernet/starlan adapter 15 */ 16 17 /* 18 * Memory Select Register (MSR) 19 */ 20 union we_mem_sel { 21 struct memory_decode { 22 u_char msd_addr:6, /* Memory decode bits */ 23 msd_enable:1, /* Memory (RAM) enable */ 24 msd_reset:1; /* Software reset */ 25 } msd_decode; 26 #define ms_addr msd_decode.msd_addr 27 #define ms_enable msd_decode.msd_enable 28 #define ms_reset msd_decode.msd_reset 29 u_char ms_byte; /* entire byte */ 30 }; 31 32 /* 33 * receive ring discriptor 34 * 35 * The National Semiconductor DS8390 Network interface controller uses 36 * the following receive ring headers. The way this works is that the 37 * memory on the interface card is chopped up into 256 bytes blocks. 38 * A contiguous portion of those blocks are marked for receive packets 39 * by setting start and end block #'s in the NIC. For each packet that 40 * is put into the receive ring, one of these headers (4 bytes each) is 41 * tacked onto the front. 42 */ 43 struct we_ring { 44 struct wer_status { /* received packet status */ 45 u_char rs_prx:1, /* packet received intack */ 46 rs_crc:1, /* crc error */ 47 rs_fae:1, /* frame alignment error */ 48 rs_fo:1, /* fifo overrun */ 49 rs_mpa:1, /* packet received intack */ 50 rs_phy:1, /* packet received intack */ 51 rs_dis:1, /* packet received intack */ 52 rs_dfr:1; /* packet received intack */ 53 } we_rcv_status; /* received packet status */ 54 u_char we_next_packet; /* pointer to next packet */ 55 u_short we_count; /* bytes in packet (length + 4) */ 56 }; 57 58 /* 59 * Command word definition 60 */ 61 union we_command { 62 struct command_decode { 63 u_char csd_stp:1, /* STOP! */ 64 csd_sta:1, /* START! */ 65 csd_txp:1, /* Transmit packet */ 66 csd_rd:3, /* Remote DMA command */ 67 csd_ps:2; /* Page select */ 68 } csd_decode; 69 #define cs_stp csd_decode.csd_stp 70 #define cs_sta csd_decode.csd_sta 71 #define cs_txp csd_decode.csd_txp 72 #define cs_rd csd_decode.csd_rd 73 #define cs_ps csd_decode.csd_ps 74 u_char cs_byte; /* entire command byte */ 75 }; 76 77 /* 78 * Interrupt status definition 79 */ 80 union we_interrupt { 81 struct interrupt_decode { 82 u_char isd_prx:1, /* Packet received */ 83 isd_ptx:1, /* Packet transmitted */ 84 isd_rxe:1, /* Receive error */ 85 isd_txe:1, /* Transmit error */ 86 isd_ovw:1, /* Overwrite warning */ 87 isd_cnt:1, /* Counter overflow */ 88 isd_rdc:1, /* Remote DMA complete */ 89 isd_rst:1; /* Reset status */ 90 } isd_decode; 91 #define is_prx isd_decode.isd_prx 92 #define is_ptx isd_decode.isd_ptx 93 #define is_rxe isd_decode.isd_rxe 94 #define is_txe isd_decode.isd_txe 95 #define is_ovw isd_decode.isd_ovw 96 #define is_cnt isd_decode.isd_cnt 97 #define is_rdc isd_decode.isd_rdc 98 #define is_rst isd_decode.isd_rst 99 u_char is_byte; /* entire interrupt byte */ 100 }; 101 102 /* 103 * Status word definition (transmit) 104 */ 105 union wet_status { 106 struct tstat { 107 u_char tsd_ptx:1, /* Packet transmitted intack */ 108 tsd_dfr:1, /* Non deferred transmition */ 109 tsd_col:1, /* Transmit Collided */ 110 tsd_abt:1, /* Transmit Aborted (coll > 16) */ 111 tsd_crs:1, /* Carrier Sense Lost */ 112 tsd_fu:1, /* Fifo Underrun */ 113 tsd_chd:1, /* CD Heartbeat */ 114 tsd_owc:1; /* Out of Window Collision */ 115 } tsd_decode; 116 #define ts_ptx tsd_decode.tsd_ptx 117 #define ts_dfr tsd_decode.tsd_dfr 118 #define ts_col tsd_decode.tsd_col 119 #define ts_abt tsd_decode.tsd_abt 120 #define ts_crs tsd_decode.tsd_crs 121 #define ts_fu tsd_decode.tsd_fu 122 #define ts_chd tsd_decode.tsd_chd 123 #define ts_owc tsd_decode.tsd_owc 124 u_char ts_byte; /* entire transmit byte */ 125 }; 126 127 /* 128 * General constant definitions 129 */ 130 #define WD_STARLAN 0x02 /* WD8003S Identification */ 131 #define WD_ETHER 0x03 /* WD8003E Identification */ 132 #define WD_ETHER2 0x05 /* WD8003EBT Identification */ 133 #define WD_CHECKSUM 0xFF /* Checksum byte */ 134 #define WD_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 135 #define WD_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 136 #define WD_ROM_OFFSET 8 /* i/o base offset to ROM */ 137 #define WD_IO_PORTS 32 /* # of i/o addresses used */ 138 #define WD_NIC_OFFSET 16 /* i/o base offset to NIC */ 139 140 /* 141 * Page register offset values 142 */ 143 #define WD_P0_COMMAND 0x00 /* Command register */ 144 #define WD_P0_PSTART 0x01 /* Page Start register */ 145 #define WD_P0_PSTOP 0x02 /* Page Stop register */ 146 #define WD_P0_BNRY 0x03 /* Boundary Pointer */ 147 #define WD_P0_TSR 0x04 /* Transmit Status (read-only) */ 148 #define WD_P0_TPSR WD_P0_TSR /* Transmit Page (write-only) */ 149 #define WD_P0_TBCR0 0x05 /* Transmit Byte count, low WO */ 150 #define WD_P0_TBCR1 0x06 /* Transmit Byte count, high WO */ 151 #define WD_P0_ISR 0x07 /* Interrupt status register */ 152 #define WD_P0_RBCR0 0x0A /* Remote byte count low WO */ 153 #define WD_P0_RBCR1 0x0B /* Remote byte count high WO */ 154 #define WD_P0_RSR 0x0C /* Receive status RO */ 155 #define WD_P0_RCR WD_P0_RSR /* Receive configuration WO */ 156 #define WD_P0_TCR 0x0D /* Transmit configuration WO */ 157 #define WD_P0_DCR 0x0E /* Data configuration WO */ 158 #define WD_P0_IMR 0x0F /* Interrupt masks WO */ 159 #define WD_P1_COMMAND 0x00 /* Command register */ 160 #define WD_P1_PAR0 0x01 /* Physical address register 0 */ 161 #define WD_P1_PAR1 0x02 /* Physical address register 1 */ 162 #define WD_P1_PAR2 0x03 /* Physical address register 2 */ 163 #define WD_P1_PAR3 0x04 /* Physical address register 3 */ 164 #define WD_P1_PAR4 0x05 /* Physical address register 4 */ 165 #define WD_P1_PAR5 0x06 /* Physical address register 5 */ 166 #define WD_P1_CURR 0x07 /* Current page (receive unit) */ 167 #define WD_P1_MAR0 0x08 /* Multicast address register 0 */ 168 169 /* 170 * Configuration constants (receive unit) 171 */ 172 #define WD_R_SEP 0x01 /* Save error packets */ 173 #define WD_R_AR 0x02 /* Accept Runt packets */ 174 #define WD_R_AB 0x04 /* Accept Broadcast packets */ 175 #define WD_R_AM 0x08 /* Accept Multicast packets */ 176 #define WD_R_PRO 0x10 /* Promiscuous physical */ 177 #define WD_R_MON 0x20 /* Monitor mode */ 178 #define WD_R_RES1 0x40 /* reserved... */ 179 #define WD_R_RES2 0x80 /* reserved... */ 180 #define WD_R_CONFIG (WD_R_AB) 181 182 /* 183 * Configuration constants (transmit unit) 184 */ 185 #define WD_T_CRC 0x01 /* Inhibit CRC */ 186 #define WD_T_LB0 0x02 /* Encoded Loopback Control */ 187 #define WD_T_LB1 0x04 /* Encoded Loopback Control */ 188 #define WD_T_ATD 0x08 /* Auto Transmit Disable */ 189 #define WD_T_OFST 0x10 /* Collision Offset Enable */ 190 #define WD_T_RES1 0x20 /* reserved... */ 191 #define WD_T_RES2 0x40 /* reserved... */ 192 #define WD_T_RES3 0x80 /* reserved... */ 193 #define WD_T_CONFIG (0) 194 195 /* 196 * Configuration constants (data unit) 197 */ 198 #define WD_D_WTS 0x01 /* Word Transfer Select */ 199 #define WD_D_BOS 0x02 /* Byte Order Select */ 200 #define WD_D_LAS 0x04 /* Long Address Select */ 201 #define WD_D_BMS 0x08 /* Burst Mode Select */ 202 #define WD_D_AR 0x10 /* Autoinitialize Remote */ 203 #define WD_D_FT0 0x20 /* Fifo Threshold Select */ 204 #define WD_D_FT1 0x40 /* Fifo Threshold Select */ 205 #define WD_D_RES 0x80 /* reserved... */ 206 #define WD_D_CONFIG (WD_D_FT1|WD_D_BMS) 207 208 /* 209 * Configuration constants (interrupt mask register) 210 */ 211 #define WD_I_PRXE 0x01 /* Packet received enable */ 212 #define WD_I_PTXE 0x02 /* Packet transmitted enable */ 213 #define WD_I_RXEE 0x04 /* Receive error enable */ 214 #define WD_I_TXEE 0x08 /* Transmit error enable */ 215 #define WD_I_OVWE 0x10 /* Overwrite warning enable */ 216 #define WD_I_CNTE 0x20 /* Counter overflow enable */ 217 #define WD_I_RDCE 0x40 /* Dma complete enable */ 218 #define WD_I_RES 0x80 /* reserved... */ 219 #define WD_I_CONFIG (WD_I_PRXE|WD_I_PTXE|WD_I_RXEE|WD_I_TXEE) 220