1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)isa.h 5.8 (Berkeley) 07/23/92 11 */ 12 13 /* 14 * ISA Bus conventions 15 */ 16 17 /*#ifndef LOCORE 18 unsigned char inb(), rtcin(); 19 void outb(); 20 #endif*/ 21 22 #ifndef LOCORE 23 unsigned char rtcin(); 24 25 #define inb(io) ({u_short iop; register u_char rtn; \ 26 iop = (io); \ 27 asm (" movl %1,%%edx; inb %%al,%%dx; movzbl %%al,%0 " \ 28 : "=r" (rtn) \ 29 : "g" (iop) \ 30 : "ax,dx"); \ 31 rtn; \ 32 }) 33 34 #define outb(io, v) ({u_short iop; u_char val; \ 35 iop = (io); \ 36 val = (v); \ 37 asm (" movl %1,%%edx; movl %0,%%eax; outb %%dx,%%al " \ 38 : \ 39 : "g" (val) \ 40 : "g" (iop) \ 41 : "ax,dx"); \ 42 }) 43 44 #endif 45 /* 46 * Input / Output Port Assignments 47 */ 48 49 #ifndef IO_BEGIN 50 #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 51 52 /* CPU Board */ 53 #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 54 #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 55 #define IO_TIMER1 0x040 /* 8252 Timer #1 */ 56 #define IO_TIMER2 0x048 /* 8252 Timer #2 */ 57 #define IO_KBD 0x060 /* 8042 Keyboard */ 58 #define IO_RTC 0x070 /* RTC */ 59 #define IO_NMI IO_RTC /* NMI Control */ 60 #define IO_DMAPG 0x080 /* DMA Page Registers */ 61 #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 62 #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 63 #define IO_NPX 0x0F0 /* Numeric Coprocessor */ 64 65 /* Cards */ 66 /* 0x100 - 0x16F Open */ 67 68 #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ 69 70 /* 0x178 - 0x1EF Open */ 71 72 #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ 73 #define IO_GAME 0x200 /* Game Controller */ 74 75 /* 0x208 - 0x277 Open */ 76 77 #define IO_LPT2 0x278 /* Parallel Port #2 */ 78 79 /* 0x280 - 0x2F7 Open */ 80 81 #define IO_COM2 0x2f8 /* COM2 i/o address */ 82 83 /* 0x300 - 0x36F Open */ 84 85 #define IO_FD2 0x370 /* secondary base i/o address */ 86 #define IO_LPT1 0x378 /* Parallel Port #1 */ 87 88 /* 0x380 - 0x3AF Open */ 89 90 #define IO_MDA 0x3B0 /* Monochome Adapter */ 91 #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 92 #define IO_VGA 0x3C0 /* E/VGA Ports */ 93 #define IO_CGA 0x3D0 /* CGA Ports */ 94 95 /* 0x3E0 - 0x3EF Open */ 96 97 #define IO_FD1 0x3f0 /* primary base i/o address */ 98 #define IO_COM1 0x3f8 /* COM1 i/o address */ 99 100 #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 101 #endif IO_ISABEGIN 102 103 /* 104 * Input / Output Memory Physical Addresses 105 */ 106 107 #ifndef IOM_BEGIN 108 #define IOM_BEGIN 0xa0000 /* Start of I/O Memory "hole" */ 109 #define IOM_END 0xFFFFF /* End of I/O Memory "hole" */ 110 #endif IOM_BEGIN 111 112 /* 113 * RAM Physical Address Space (ignoring the above mentioned "hole") 114 */ 115 116 #ifndef RAM_BEGIN 117 #define RAM_BEGIN 0x000000 /* Start of RAM Memory */ 118 #define RAM_END 0xFFFFFF /* End of RAM Memory */ 119 #endif IOM_BEGIN 120 121 /* 122 * Oddball Physical Memory Addresses 123 */ 124 #ifndef COMPAQ_RAMRELOC 125 #define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 126 #define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ 127 #define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 128 #define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ 129 #endif COMPAQ_RAMRELOC 130