1 /* 2 * Copyright (c) 1982, 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * from: hp300/dev/if_lereg.h 7.4 (Berkeley) 7/6/92 8 * 9 * @(#)if_lereg.h 7.2 (Berkeley) 07/23/92 10 */ 11 12 #ifdef KERNEL 13 #include "iotypes.h" /* XXX */ 14 #else 15 #include <luna68k/dev/iotypes.h> /* XXX */ 16 #endif 17 18 #define LEID 21 19 20 #define LEMTU 1518 21 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 22 #define LERBUF 8 23 #define LERBUFLOG2 3 24 #define LE_RLEN (LERBUFLOG2 << 13) 25 #define LETBUF 2 26 #define LETBUFLOG2 1 27 #define LE_TLEN (LETBUFLOG2 << 13) 28 29 /* 30 * LANCE registers. 31 */ 32 struct lereg0 { 33 u_char ler0_pad0; 34 vu_char ler0_id; /* ID */ 35 u_char ler0_pad1; 36 vu_char ler0_status; /* interrupt enable/status */ 37 }; 38 39 struct lereg1 { 40 u_short ler1_rdp; /* data port */ 41 u_short ler1_rap; /* register select port */ 42 }; 43 44 /* 45 * Overlayed on 16K dual-port RAM. 46 * Current size is 15,284 bytes with 8 x 1518 receive buffers and 47 * 2 x 1518 transmit buffers. 48 */ 49 struct lereg2 { 50 /* init block */ 51 u_short ler2_mode; /* +0x0000 */ 52 u_char ler2_padr[6]; /* +0x0002 */ 53 u_long ler2_ladrf[2]; /* +0x0008 */ 54 u_short ler2_rdra; /* +0x0010 */ 55 u_short ler2_rlen; /* +0x0012 */ 56 u_short ler2_tdra; /* +0x0014 */ 57 u_short ler2_tlen; /* +0x0016 */ 58 /* receive message descriptors */ 59 struct lermd { /* +0x0018 */ 60 u_short rmd0; 61 u_short rmd1; 62 short rmd2; 63 u_short rmd3; 64 } ler2_rmd[LERBUF]; 65 /* transmit message descriptors */ 66 struct letmd { /* +0x0058 */ 67 u_short tmd0; 68 u_short tmd1; 69 short tmd2; 70 u_short tmd3; 71 } ler2_tmd[LETBUF]; 72 char ler2_rbuf[LERBUF][LEMTU]; /* +0x0068 */ 73 char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD8 */ 74 }; 75 76 /* 77 * Control and status bits -- lereg0 78 */ 79 #define LE_IE 0x80 /* interrupt enable */ 80 #define LE_IR 0x40 /* interrupt requested */ 81 #define LE_LOCK 0x08 /* lock status register */ 82 #define LE_ACK 0x04 /* ack of lock */ 83 #define LE_JAB 0x02 /* loss of tx clock (???) */ 84 85 /* 86 * Control and status bits -- lereg1 87 */ 88 #define LE_CSR0 0 89 #define LE_CSR1 1 90 #define LE_CSR2 2 91 #define LE_CSR3 3 92 93 #define LE_SERR 0x8000 94 #define LE_BABL 0x4000 95 #define LE_CERR 0x2000 96 #define LE_MISS 0x1000 97 #define LE_MERR 0x0800 98 #define LE_RINT 0x0400 99 #define LE_TINT 0x0200 100 #define LE_IDON 0x0100 101 #define LE_INTR 0x0080 102 #define LE_INEA 0x0040 103 #define LE_RXON 0x0020 104 #define LE_TXON 0x0010 105 #define LE_TDMD 0x0008 106 #define LE_STOP 0x0004 107 #define LE_STRT 0x0002 108 #define LE_INIT 0x0001 109 110 #define LE_BSWP 0x4 111 #define LE_MODE 0x0 112 113 /* 114 * Control and status bits -- lereg2 115 */ 116 #define LE_OWN 0x8000 117 #define LE_ERR 0x4000 118 #define LE_STP 0x0200 119 #define LE_ENP 0x0100 120 121 #define LE_FRAM 0x2000 122 #define LE_OFLO 0x1000 123 #define LE_CRC 0x0800 124 #define LE_RBUFF 0x0400 125 #define LE_MORE 0x1000 126 #define LE_ONE 0x0800 127 #define LE_DEF 0x0400 128 #define LE_TBUFF 0x8000 129 #define LE_UFLO 0x4000 130 #define LE_LCOL 0x1000 131 #define LE_LCAR 0x0800 132 #define LE_RTRY 0x0400 133