1 /* 2 * Copyright (c) 1982, 1990, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * from: hp300/dev/if_lereg.h 7.5 (Berkeley) 10/11/92 8 * 9 * @(#)if_lereg.h 8.1 (Berkeley) 06/10/93 10 */ 11 12 #include <luna68k/dev/iotypes.h> /* XXX */ 13 14 #define LEID 21 15 16 #define LEMTU 1518 17 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 18 #define LERBUF 8 19 #define LERBUFLOG2 3 20 #define LE_RLEN (LERBUFLOG2 << 13) 21 #define LETBUF 2 22 #define LETBUFLOG2 1 23 #define LE_TLEN (LETBUFLOG2 << 13) 24 25 /* 26 * LANCE registers. 27 */ 28 struct lereg0 { 29 u_char ler0_pad0; 30 vu_char ler0_id; /* ID */ 31 u_char ler0_pad1; 32 vu_char ler0_status; /* interrupt enable/status */ 33 }; 34 35 struct lereg1 { 36 u_short ler1_rdp; /* data port */ 37 u_short ler1_rap; /* register select port */ 38 }; 39 40 /* 41 * Overlayed on 16K dual-port RAM. 42 * Current size is 15,284 bytes with 8 x 1518 receive buffers and 43 * 2 x 1518 transmit buffers. 44 */ 45 struct lereg2 { 46 /* init block */ 47 u_short ler2_mode; /* +0x0000 */ 48 u_char ler2_padr[6]; /* +0x0002 */ 49 u_long ler2_ladrf[2]; /* +0x0008 */ 50 u_short ler2_rdra; /* +0x0010 */ 51 u_short ler2_rlen; /* +0x0012 */ 52 u_short ler2_tdra; /* +0x0014 */ 53 u_short ler2_tlen; /* +0x0016 */ 54 /* receive message descriptors */ 55 struct lermd { /* +0x0018 */ 56 u_short rmd0; 57 u_short rmd1; 58 short rmd2; 59 u_short rmd3; 60 } ler2_rmd[LERBUF]; 61 /* transmit message descriptors */ 62 struct letmd { /* +0x0058 */ 63 u_short tmd0; 64 u_short tmd1; 65 short tmd2; 66 u_short tmd3; 67 } ler2_tmd[LETBUF]; 68 char ler2_rbuf[LERBUF][LEMTU]; /* +0x0068 */ 69 char ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD8 */ 70 }; 71 72 /* 73 * Control and status bits -- lereg0 74 */ 75 #define LE_IE 0x80 /* interrupt enable */ 76 #define LE_IR 0x40 /* interrupt requested */ 77 #define LE_LOCK 0x08 /* lock status register */ 78 #define LE_ACK 0x04 /* ack of lock */ 79 #define LE_JAB 0x02 /* loss of tx clock (???) */ 80 81 /* 82 * Control and status bits -- lereg1 83 */ 84 #define LE_CSR0 0 85 #define LE_CSR1 1 86 #define LE_CSR2 2 87 #define LE_CSR3 3 88 89 #define LE_SERR 0x8000 90 #define LE_BABL 0x4000 91 #define LE_CERR 0x2000 92 #define LE_MISS 0x1000 93 #define LE_MERR 0x0800 94 #define LE_RINT 0x0400 95 #define LE_TINT 0x0200 96 #define LE_IDON 0x0100 97 #define LE_INTR 0x0080 98 #define LE_INEA 0x0040 99 #define LE_RXON 0x0020 100 #define LE_TXON 0x0010 101 #define LE_TDMD 0x0008 102 #define LE_STOP 0x0004 103 #define LE_STRT 0x0002 104 #define LE_INIT 0x0001 105 106 #define LE_BSWP 0x4 107 #define LE_MODE 0x0 108 109 /* 110 * Control and status bits -- lereg2 111 */ 112 #define LE_OWN 0x8000 113 #define LE_ERR 0x4000 114 #define LE_STP 0x0200 115 #define LE_ENP 0x0100 116 117 #define LE_FRAM 0x2000 118 #define LE_OFLO 0x1000 119 #define LE_CRC 0x0800 120 #define LE_RBUFF 0x0400 121 #define LE_MORE 0x1000 122 #define LE_ONE 0x0800 123 #define LE_DEF 0x0400 124 #define LE_TBUFF 0x8000 125 #define LE_UFLO 0x4000 126 #define LE_LCOL 0x1000 127 #define LE_LCAR 0x0800 128 #define LE_RTRY 0x0400 129