1 /* 2 * Copyright (c) 1992 OMRON Corporation. 3 * Copyright (c) 1992 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * OMRON Corporation. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)sioreg.h 7.1 (Berkeley) 06/15/92 12 */ 13 14 /* 15 * sioreg.h -- NEC uPD7201A Hardware Discription 16 * by A.Fujita, NOV-26-1991 17 */ 18 19 struct siodevice { 20 volatile u_char sio_data; 21 u_char sio_pad1; 22 volatile u_char sio_cmd; 23 u_char sio_pad2; 24 }; 25 26 #define sio_stat sio_cmd 27 28 #define splsio spl6 29 30 31 #define REG(u, r) ( (u << 4) | r ) 32 #define CHANNEL(r) ( r >> 4 ) 33 #define REGNO(r) ( r & 0x07 ) 34 #define isStatusReg(r) ( r & 0x08 ) 35 36 #define WR0 0x00 37 #define WR1 0x01 38 #define WR2 0x02 39 #define WR3 0x03 40 #define WR4 0x04 41 #define WR5 0x05 42 #define WR6 0x06 43 #define WR7 0x07 44 45 #define WR2A 0x02 46 #define WR2B 0x12 47 48 #define RR0 0x08 49 #define RR1 0x09 50 #define RR2 0x0A 51 #define RR3 0x0B 52 #define RR4 0x0C 53 54 #define RR2A 0x0A 55 #define RR2B 0x1A 56 57 #define WR0_NOP 0x00 /* No Operation */ 58 #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */ 59 #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */ 60 #define WR0_CHANRST 0x18 /* Channel Reset */ 61 #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */ 62 #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */ 63 #define WR0_ERRRST 0x30 /* Error Reset */ 64 #define WR0_ENDINTR 0x38 /* End of Interrupt */ 65 66 #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */ 67 #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */ 68 #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */ 69 #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */ 70 #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */ 71 #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */ 72 #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */ 73 74 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ 75 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ 76 #define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */ 77 #define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */ 78 #define WR2_VEC86 0x10 /* 8086 Vectored */ 79 #define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */ 80 81 #define WR3_RXENBL 0x01 /* Rx Enable */ 82 #define WR3_RXCRC 0x08 /* Rx CRC Check */ 83 #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */ 84 #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */ 85 #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */ 86 #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */ 87 #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */ 88 89 #define WR4_NPARITY 0x00 /* No Parity */ 90 #define WR4_OPARITY 0x01 /* Parity Odd */ 91 #define WR4_EPARITY 0x02 /* Parity Even */ 92 #define WR4_STOP1 0x04 /* Stop Bits (1bit) */ 93 #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */ 94 #define WR4_STOP2 0x0c /* Stop Bits (2bit) */ 95 #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */ 96 #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */ 97 #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */ 98 99 #define WR5_TXCRC 0x01 /* Tx CRC Check */ 100 #define WR5_REQSND 0x02 /* Request To Send (LOW) */ 101 #define WR5_TXENBL 0x08 /* Transmit Enable */ 102 #define WR5_BREAK 0x10 /* Send Break */ 103 #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */ 104 #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */ 105 #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */ 106 #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */ 107 108 #define RR0_RXAVAIL 0x01 /* Rx Character Available */ 109 #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */ 110 #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */ 111 #define RR0_BREAK 0x80 /* Break Detected */ 112 113 #define RR1_PARITY 0x10 /* Parity Error */ 114 #define RR1_OVERRUN 0x20 /* Data Over Run */ 115 #define RR1_FRAMING 0x40 /* Framing Error */ 116 117 #define RR_RXRDY 0x0100 /* Rx Character Available */ 118 #define RR_INTRPEND 0x0200 /* Interrupt Pending (Channel-A Only) */ 119 #define RR_TXRDY 0x0400 /* Tx Buffer Empty */ 120 #define RR_BREAK 0x8000 /* Break Detected */ 121 #define RR_PARITY 0x0010 /* Parity Error */ 122 #define RR_OVERRUN 0x0020 /* Data Over Run */ 123 #define RR_FRAMING 0x0040 /* Framing Error */ 124