1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992 OMRON Corporation. 4 * Copyright (c) 1982, 1990, 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * %sccs.include.redist.c% 12 * 13 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 14 * from: hp300/include/cpu.h 8.2 (Berkeley) 9/23/93 15 * 16 * @(#)cpu.h 8.5 (Berkeley) 01/05/94 17 */ 18 19 /* 20 * Exported definitions unique to luna/68k cpu support, 21 * taken from hp300/68k. 22 */ 23 24 /* 25 * definitions of cpu-dependent requirements 26 * referenced in generic code 27 */ 28 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 29 30 #define cpu_exec(p) /* nothing */ 31 #define cpu_swapin(p) /* nothing */ 32 #define cpu_wait(p) /* nothing */ 33 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 34 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 35 36 /* 37 * Arguments to hardclock and gatherstats encapsulate the previous 38 * machine state in an opaque clockframe. One the 68k, we use 39 * what the hardware pushes on an interrupt (but we pad the sr to a 40 * longword boundary). 41 */ 42 struct clockframe { 43 u_short sr; /* sr at time of interrupt */ 44 u_long pc; /* pc at time of interrupt */ 45 u_short vo; /* vector offset (4-word frame) */ 46 }; 47 48 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 49 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 50 #define CLKF_PC(framep) ((framep)->pc) 51 #if 0 52 /* We would like to do it this way... */ 53 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 54 #else 55 /* but until we start using PSL_M, we have to do this instead */ 56 #define CLKF_INTR(framep) (0) /* XXX */ 57 #endif 58 59 60 /* 61 * Preempt the current process if in interrupt from user mode, 62 * or after the current trap/syscall if in system mode. 63 */ 64 #define need_resched() { want_resched++; aston(); } 65 66 /* 67 * Give a profiling tick to the current process when the user profiling 68 * buffer pages are invalid. On the 68k, request an ast to send us 69 * through trap, marking the proc as needing a profiling tick. 70 */ 71 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 72 73 /* 74 * Notify the current process (p) that it has a signal pending, 75 * process as soon as possible. 76 */ 77 #define signotify(p) aston() 78 79 #define aston() (astpending++) 80 81 int astpending; /* need to trap before returning to user mode */ 82 int want_resched; /* resched() was called */ 83 84 85 /* 86 * simulated software interrupt register 87 */ 88 extern unsigned char ssir; 89 90 #define SIR_NET 0x1 91 #define SIR_CLOCK 0x2 92 93 #define siroff(x) ssir &= ~(x) 94 #define setsoftnet() ssir |= SIR_NET 95 #define setsoftclock() ssir |= SIR_CLOCK 96 97 /* 98 * CTL_MACHDEP definitions. 99 */ 100 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 101 #define CPU_MAXID 2 /* number of valid machdep ids */ 102 103 #define CTL_MACHDEP_NAMES { \ 104 { 0, 0 }, \ 105 { "console_device", CTLTYPE_STRUCT }, \ 106 } 107 108 #ifdef KERNEL 109 extern int mmutype, machineid; 110 #endif 111 112 /* values for machineid */ 113 #define LUNA_I 1 /* 20Mhz 68030 */ 114 #define LUNA_II 2 /* 25Mhz 68040 */ 115 116 /* values for mmutype (assigned for quick testing) */ 117 #define MMU_68040 -2 /* 68040 on-chip MMU */ 118 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 119 120 /* values for cpuspeed (not really related to clock speed due to caches) */ 121 #define MHZ_8 1 122 #define MHZ_16 2 123 #define MHZ_25 3 124 #define MHZ_33 4 125 #define MHZ_50 6 126 127 /* 128 * 68851 and 68030 MMU 129 */ 130 #define PMMU_LVLMASK 0x0007 131 #define PMMU_INV 0x0400 132 #define PMMU_WP 0x0800 133 #define PMMU_ALV 0x1000 134 #define PMMU_SO 0x2000 135 #define PMMU_LV 0x4000 136 #define PMMU_BE 0x8000 137 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 138 139 /* 140 * 68040 MMU 141 */ 142 #define MMU4_RES 0x001 143 #define MMU4_TTR 0x002 144 #define MMU4_WP 0x004 145 #define MMU4_MOD 0x010 146 #define MMU4_CMMASK 0x060 147 #define MMU4_SUP 0x080 148 #define MMU4_U0 0x100 149 #define MMU4_U1 0x200 150 #define MMU4_GLB 0x400 151 #define MMU4_BE 0x800 152 153 /* 680X0 function codes */ 154 #define FC_USERD 1 /* user data space */ 155 #define FC_USERP 2 /* user program space */ 156 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 157 #define FC_SUPERD 5 /* supervisor data space */ 158 #define FC_SUPERP 6 /* supervisor program space */ 159 #define FC_CPU 7 /* CPU space */ 160 161 /* fields in the 68020 cache control register */ 162 #define IC_ENABLE 0x0001 /* enable instruction cache */ 163 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 164 #define IC_CE 0x0004 /* clear instruction cache entry */ 165 #define IC_CLR 0x0008 /* clear entire instruction cache */ 166 167 /* additional fields in the 68030 cache control register */ 168 #define IC_BE 0x0010 /* instruction burst enable */ 169 #define DC_ENABLE 0x0100 /* data cache enable */ 170 #define DC_FREEZE 0x0200 /* data cache freeze */ 171 #define DC_CE 0x0400 /* clear data cache entry */ 172 #define DC_CLR 0x0800 /* clear entire data cache */ 173 #define DC_BE 0x1000 /* data burst enable */ 174 #define DC_WA 0x2000 /* write allocate */ 175 176 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 177 #define CACHE_OFF (DC_CLR|IC_CLR) 178 #define CACHE_CLR (CACHE_ON) 179 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 180 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 181 182 /* 68040 cache control register */ 183 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 184 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 185 186 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 187 #define CACHE4_OFF (0) 188