1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992 OMRON Corporation. 4 * Copyright (c) 1982, 1990, 1992 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * %sccs.include.redist.c% 12 * 13 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 14 * OMRON: $Id: cpu.h,v 1.2 92/06/14 06:27:54 moti Exp $ 15 * 16 * from: hp300/include/cpu.h 7.12 (Berkeley) 7/8/92 17 * 18 * @(#)cpu.h 7.2 (Berkeley) 07/23/92 19 */ 20 21 /* 22 * Exported definitions unique to luna/68k cpu support, taken from: 23 * hp300/68k. 24 */ 25 26 /* 27 * definitions of cpu-dependent requirements 28 * referenced in generic code 29 */ 30 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 31 32 #define cpu_exec(p) /* nothing */ 33 #define cpu_wait(p) /* nothing */ 34 #define cpu_setstack(p, ap) \ 35 (p)->p_md.md_regs[SP] = ap 36 37 /* 38 * Arguments to hardclock and gatherstats encapsulate the previous 39 * machine state in an opaque clockframe. One the 68k, we use 40 * what the hardware pushes on an interrupt (but we pad the sr to a 41 * longword boundary). 42 */ 43 struct clockframe { 44 u_short pad; /* pad to get stack aligned */ 45 u_short sr; /* sr at time of interrupt */ 46 u_long pc; /* pc at time of interrupt */ 47 u_short vo; /* vector offset (4-word frame) */ 48 }; 49 50 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 51 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 52 #define CLKF_PC(framep) ((framep)->pc) 53 #if 0 54 /* We would like to do it this way... */ 55 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 56 #else 57 /* but until we start using PSL_M, we have to do this instead */ 58 #define CLKF_INTR(framep) (0) /* XXX */ 59 #endif 60 61 62 /* 63 * Preempt the current process if in interrupt from user mode, 64 * or after the current trap/syscall if in system mode. 65 */ 66 #define need_resched() { want_resched++; aston(); } 67 68 /* 69 * Give a profiling tick to the current process when the user profiling 70 * buffer pages are invalid. On the 68k, request an ast to send us 71 * through trap, marking the proc as needing a profiling tick. 72 */ 73 #define need_proftick(p) { (p)->p_flag |= SOWEUPC; aston(); } 74 75 /* 76 * Notify the current process (p) that it has a signal pending, 77 * process as soon as possible. 78 */ 79 #define signotify(p) aston() 80 81 #define aston() (astpending++) 82 83 int astpending; /* need to trap before returning to user mode */ 84 int want_resched; /* resched() was called */ 85 86 87 /* 88 * simulated software interrupt register 89 */ 90 extern unsigned char ssir; 91 92 #define SIR_NET 0x1 93 #define SIR_CLOCK 0x2 94 95 #define siroff(x) ssir &= ~(x) 96 #define setsoftnet() ssir |= SIR_NET 97 #define setsoftclock() ssir |= SIR_CLOCK 98 99 /* values for mmutype (assigned for quick testing) */ 100 #define MMU_68040 -2 /* 68040 on-chip MMU */ 101 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 102 103 /* values for cpuspeed (not really related to clock speed due to caches) */ 104 #define MHZ_8 1 105 #define MHZ_16 2 106 #define MHZ_25 3 107 #define MHZ_33 4 108 #define MHZ_50 6 109 110 /* 111 * 68851 and 68030 MMU 112 */ 113 #define PMMU_LVLMASK 0x0007 114 #define PMMU_INV 0x0400 115 #define PMMU_WP 0x0800 116 #define PMMU_ALV 0x1000 117 #define PMMU_SO 0x2000 118 #define PMMU_LV 0x4000 119 #define PMMU_BE 0x8000 120 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 121 122 /* 123 * 68040 MMU 124 */ 125 #define MMU4_RES 0x001 126 #define MMU4_TTR 0x002 127 #define MMU4_WP 0x004 128 #define MMU4_MOD 0x010 129 #define MMU4_CMMASK 0x060 130 #define MMU4_SUP 0x080 131 #define MMU4_U0 0x100 132 #define MMU4_U1 0x200 133 #define MMU4_GLB 0x400 134 #define MMU4_BE 0x800 135 136 /* 680X0 function codes */ 137 #define FC_USERD 1 /* user data space */ 138 #define FC_USERP 2 /* user program space */ 139 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 140 #define FC_SUPERD 5 /* supervisor data space */ 141 #define FC_SUPERP 6 /* supervisor program space */ 142 #define FC_CPU 7 /* CPU space */ 143 144 /* fields in the 68020 cache control register */ 145 #define IC_ENABLE 0x0001 /* enable instruction cache */ 146 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 147 #define IC_CE 0x0004 /* clear instruction cache entry */ 148 #define IC_CLR 0x0008 /* clear entire instruction cache */ 149 150 /* additional fields in the 68030 cache control register */ 151 #define IC_BE 0x0010 /* instruction burst enable */ 152 #define DC_ENABLE 0x0100 /* data cache enable */ 153 #define DC_FREEZE 0x0200 /* data cache freeze */ 154 #define DC_CE 0x0400 /* clear data cache entry */ 155 #define DC_CLR 0x0800 /* clear entire data cache */ 156 #define DC_BE 0x1000 /* data burst enable */ 157 #define DC_WA 0x2000 /* write allocate */ 158 159 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 160 #define CACHE_OFF (DC_CLR|IC_CLR) 161 #define CACHE_CLR (CACHE_ON) 162 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 163 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 164 165 /* 68040 cache control register */ 166 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 167 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 168 169 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 170 #define CACHE4_OFF (0) 171