1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992 OMRON Corporation. 4 * Copyright (c) 1982, 1990, 1992 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * %sccs.include.redist.c% 12 * 13 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 14 * OMRON: $Id: cpu.h,v 1.2 92/06/14 06:27:54 moti Exp $ 15 * 16 * @(#)cpu.h 7.1 (Berkeley) 06/15/92 17 */ 18 19 /* 20 * Exported definitions unique to luna/68k cpu support, taken from: 21 * hp300/68k. 22 */ 23 24 /* 25 * definitions of cpu-dependent requirements 26 * referenced in generic code 27 */ 28 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 29 30 /* 31 * function vs. inline configuration; 32 * these are defined to get generic functions 33 * rather than inline or machine-dependent implementations 34 */ 35 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 36 #undef NEED_FFS /* don't need ffs function */ 37 #undef NEED_BCMP /* don't need bcmp function */ 38 #undef NEED_STRLEN /* don't need strlen function */ 39 40 #define cpu_exec(p) /* nothing */ 41 #define cpu_wait(p) /* nothing */ 42 #define cpu_setstack(p, ap) \ 43 (p)->p_md.md_regs[SP] = ap 44 45 /* 46 * Arguments to hardclock, softclock and gatherstats 47 * encapsulate the previous machine state in an opaque 48 * clockframe; for 68k, use just what the hardware 49 * leaves on the stack. 50 */ 51 typedef struct intrframe { 52 char *pc; 53 int ps; 54 } clockframe; 55 56 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 57 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 58 #define CLKF_PC(framep) ((framep)->pc) 59 60 61 /* 62 * Preempt the current process if in interrupt from user mode, 63 * or after the current trap/syscall if in system mode. 64 */ 65 #define need_resched() { want_resched++; aston(); } 66 67 /* 68 * Give a profiling tick to the current process from the softclock 69 * interrupt. On 68k, request an ast to send us through trap(), 70 * marking the proc as needing a profiling tick. 71 */ 72 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 73 74 /* 75 * Notify the current process (p) that it has a signal pending, 76 * process as soon as possible. 77 */ 78 #define signotify(p) aston() 79 80 #define aston() (astpending++) 81 82 int astpending; /* need to trap before returning to user mode */ 83 int want_resched; /* resched() was called */ 84 85 86 /* 87 * simulated software interrupt register 88 */ 89 extern unsigned char ssir; 90 91 #define SIR_NET 0x1 92 #define SIR_CLOCK 0x2 93 94 #define siroff(x) ssir &= ~(x) 95 #define setsoftnet() ssir |= SIR_NET 96 #define setsoftclock() ssir |= SIR_CLOCK 97 98 /* values for mmutype (assigned for quick testing) */ 99 #define MMU_68040 -2 /* 68040 on-chip MMU */ 100 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 101 102 /* values for cpuspeed (not really related to clock speed due to caches) */ 103 #define MHZ_8 1 104 #define MHZ_16 2 105 #define MHZ_25 3 106 #define MHZ_33 4 107 #define MHZ_50 6 108 109 /* 110 * 68851 and 68030 MMU 111 */ 112 #define PMMU_LVLMASK 0x0007 113 #define PMMU_INV 0x0400 114 #define PMMU_WP 0x0800 115 #define PMMU_ALV 0x1000 116 #define PMMU_SO 0x2000 117 #define PMMU_LV 0x4000 118 #define PMMU_BE 0x8000 119 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 120 121 /* 122 * 68040 MMU 123 */ 124 #define MMU4_RES 0x001 125 #define MMU4_TTR 0x002 126 #define MMU4_WP 0x004 127 #define MMU4_MOD 0x010 128 #define MMU4_CMMASK 0x060 129 #define MMU4_SUP 0x080 130 #define MMU4_U0 0x100 131 #define MMU4_U1 0x200 132 #define MMU4_GLB 0x400 133 #define MMU4_BE 0x800 134 135 /* 680X0 function codes */ 136 #define FC_USERD 1 /* user data space */ 137 #define FC_USERP 2 /* user program space */ 138 #define FC_PURGE 3 /* HPMMU: clear TLB entries */ 139 #define FC_SUPERD 5 /* supervisor data space */ 140 #define FC_SUPERP 6 /* supervisor program space */ 141 #define FC_CPU 7 /* CPU space */ 142 143 /* fields in the 68020 cache control register */ 144 #define IC_ENABLE 0x0001 /* enable instruction cache */ 145 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 146 #define IC_CE 0x0004 /* clear instruction cache entry */ 147 #define IC_CLR 0x0008 /* clear entire instruction cache */ 148 149 /* additional fields in the 68030 cache control register */ 150 #define IC_BE 0x0010 /* instruction burst enable */ 151 #define DC_ENABLE 0x0100 /* data cache enable */ 152 #define DC_FREEZE 0x0200 /* data cache freeze */ 153 #define DC_CE 0x0400 /* clear data cache entry */ 154 #define DC_CLR 0x0800 /* clear entire data cache */ 155 #define DC_BE 0x1000 /* data burst enable */ 156 #define DC_WA 0x2000 /* write allocate */ 157 158 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 159 #define CACHE_OFF (DC_CLR|IC_CLR) 160 #define CACHE_CLR (CACHE_ON) 161 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 162 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 163 164 /* 68040 cache control register */ 165 #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ 166 #define DC4_ENABLE 0x80000000 /* data cache enable bit */ 167 168 #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) 169 #define CACHE4_OFF (0) 170