1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992 OMRON Corporation. 4 * Copyright (c) 1982, 1986, 1990, 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * %sccs.include.redist.c% 12 * 13 * from: Utah $Hdr: pte.h 1.13 92/01/20$ 14 * from: hp300/hp300/pte.h 7.4 (Berkeley) 6/5/92 15 * 16 * @(#)pte.h 8.1 (Berkeley) 06/10/93 17 */ 18 19 /* 20 * LUNA68K hardware segment/page table entries 21 */ 22 23 struct ste { 24 unsigned int sg_pfnum:20; /* page table frame number */ 25 unsigned int :8; /* reserved at 0 */ 26 unsigned int :1; /* reserved at 1 */ 27 unsigned int sg_prot:1; /* write protect bit */ 28 unsigned int sg_v:2; /* valid bits */ 29 }; 30 31 struct ste40 { 32 unsigned int sg_ptaddr:24; /* page table page addr */ 33 unsigned int :4; /* reserved at 0 */ 34 unsigned int sg_u; /* hardware modified (dirty) bit */ 35 unsigned int sg_prot:1; /* write protect bit */ 36 unsigned int sg_v:2; /* valid bits */ 37 }; 38 39 struct pte { 40 unsigned int pg_pfnum:20; /* page frame number or 0 */ 41 unsigned int :3; 42 unsigned int pg_w:1; /* is wired */ 43 unsigned int :1; /* reserved at zero */ 44 unsigned int pg_ci:1; /* cache inhibit bit */ 45 unsigned int :1; /* reserved at zero */ 46 unsigned int pg_m:1; /* hardware modified (dirty) bit */ 47 unsigned int pg_u:1; /* hardware used (reference) bit */ 48 unsigned int pg_prot:1; /* write protect bit */ 49 unsigned int pg_v:2; /* valid bit */ 50 }; 51 52 typedef struct ste st_entry_t; /* segment table entry */ 53 typedef struct pte pt_entry_t; /* Mach page table entry */ 54 55 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 56 #define ST_ENTRY_NULL ((st_entry_t *) 0) 57 58 #define SG_V 0x00000002 /* segment is valid */ 59 #define SG_NV 0x00000000 60 #define SG_PROT 0x00000004 /* access protection mask */ 61 #define SG_RO 0x00000004 62 #define SG_RW 0x00000000 63 #define SG_U 0x00000008 /* modified bit (68040) */ 64 #define SG_FRAME 0xfffff000 65 #define SG_IMASK 0xffc00000 66 #define SG_ISHIFT 22 67 #define SG_PMASK 0x003ff000 68 #define SG_PSHIFT 12 69 70 /* 68040 additions */ 71 #define SG4_MASK1 0xfe000000 72 #define SG4_SHIFT1 25 73 #define SG4_MASK2 0x01fc0000 74 #define SG4_SHIFT2 18 75 #define SG4_MASK3 0x0003f000 76 #define SG4_SHIFT3 12 77 #define SG4_ADDR1 0xfffffe00 78 #define SG4_ADDR2 0xffffff00 79 #define SG4_LEV1SIZE 128 80 #define SG4_LEV2SIZE 128 81 #define SG4_LEV3SIZE 64 82 83 #define PG_V 0x00000001 84 #define PG_NV 0x00000000 85 #define PG_PROT 0x00000004 86 #define PG_U 0x00000008 87 #define PG_M 0x00000010 88 #define PG_W 0x00000100 89 #define PG_RO 0x00000004 90 #define PG_RW 0x00000000 91 #define PG_FRAME 0xfffff000 92 #define PG_CI 0x00000040 93 #define PG_SHIFT 12 94 #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 95 96 /* 68040 additions */ 97 #define PG_CMASK 0x00000060 /* cache mode mask */ 98 #define PG_CWT 0x00000000 /* writethrough caching */ 99 #define PG_CCB 0x00000020 /* copyback caching */ 100 #define PG_CIS 0x00000040 /* cache inhibited serialized */ 101 #define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 102 #define PG_SO 0x00000080 /* supervisor only */ 103 104 #define LUNA_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t)) 105 /* user process segment table size */ 106 #define LUNA_MAX_PTSIZE 0x400000 /* max size of UPT */ 107 #define LUNA_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */ 108 #define LUNA_PTBASE 0x10000000 /* UPT map base address */ 109 #define LUNA_PTMAXSIZE 0x20000000 /* UPT map maximum size */ 110 111 /* 112 * Kernel virtual address to page table entry and to physical address. 113 */ 114 #define kvtopte(va) \ 115 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 116 #define ptetokv(pt) \ 117 ((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 118 #define kvtophys(va) \ 119 ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET)) 120 121