1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992 OMRON Corporation. 4 * Copyright (c) 1982, 1986, 1990, 1992 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * %sccs.include.redist.c% 12 * 13 * from: Utah $Hdr: pte.h 1.13 92/01/20$ 14 * OMRON: $Id: pte.h,v 1.2 92/06/14 06:22:11 moti Exp $ 15 * 16 * from: hp300/hp300/pte.h 7.1 (Berkeley) 6/4/92 17 * 18 * @(#)pte.h 7.1 (Berkeley) 06/15/92 19 */ 20 21 /* 22 * LUNA68K hardware segment/page table entries 23 */ 24 25 struct ste { 26 unsigned int sg_pfnum:20; /* page table frame number */ 27 unsigned int :8; /* reserved at 0 */ 28 unsigned int :1; /* reserved at 1 */ 29 unsigned int sg_prot:1; /* write protect bit */ 30 unsigned int sg_v:2; /* valid bits */ 31 }; 32 33 struct pte { 34 unsigned int pg_pfnum:20; /* page frame number or 0 */ 35 unsigned int :3; 36 unsigned int pg_w:1; /* is wired */ 37 unsigned int :1; /* reserved at zero */ 38 unsigned int pg_ci:1; /* cache inhibit bit */ 39 unsigned int :1; /* reserved at zero */ 40 unsigned int pg_m:1; /* hardware modified (dirty) bit */ 41 unsigned int pg_u:1; /* hardware used (reference) bit */ 42 unsigned int pg_prot:1; /* write protect bit */ 43 unsigned int pg_v:2; /* valid bit */ 44 }; 45 46 typedef struct ste st_entry_t; /* segment table entry */ 47 typedef struct pte pt_entry_t; /* Mach page table entry */ 48 49 #define PT_ENTRY_NULL ((pt_entry_t *) 0) 50 #define ST_ENTRY_NULL ((st_entry_t *) 0) 51 52 #define SG_V 0x00000002 /* segment is valid */ 53 #define SG_NV 0x00000000 54 #define SG_PROT 0x00000004 /* access protection mask */ 55 #define SG_RO 0x00000004 56 #define SG_RW 0x00000000 57 #define SG_FRAME 0xfffff000 58 #define SG_IMASK 0xffc00000 59 #define SG_PMASK 0x003ff000 60 #define SG_ISHIFT 22 61 #define SG_PSHIFT 12 62 63 /* 68040 additions */ 64 #define SG4_MASK1 0xfe000000 65 #define SG4_SHIFT1 25 66 #define SG4_MASK2 0x01fc0000 67 #define SG4_SHIFT2 18 68 #define SG4_MASK3 0x0003f000 69 #define SG4_SHIFT3 12 70 #define SG4_ADDR1 0xfffffe00 71 #define SG4_ADDR2 0xffffff00 72 #define SG4_LEV1SIZE 128 73 #define SG4_LEV2SIZE 128 74 #define SG4_LEV3SIZE 64 75 76 #define PG_V 0x00000001 77 #define PG_NV 0x00000000 78 #define PG_PROT 0x00000004 79 #define PG_U 0x00000008 80 #define PG_M 0x00000010 81 #define PG_W 0x00000100 82 #define PG_RO 0x00000004 83 #define PG_RW 0x00000000 84 #define PG_FRAME 0xfffff000 85 #define PG_CI 0x00000040 86 #define PG_SHIFT 12 87 #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT) 88 89 /* 68040 additions */ 90 #define PG_CMASK 0x00000060 /* cache mode mask */ 91 #define PG_CWT 0x00000000 /* writethrough caching */ 92 #define PG_CCB 0x00000020 /* copyback caching */ 93 #define PG_CIS 0x00000040 /* cache inhibited serialized */ 94 #define PG_CIN 0x00000060 /* cache inhibited nonserialized */ 95 #define PG_SO 0x00000080 /* supervisor only */ 96 97 #define LUNA_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t)) 98 /* user process segment table size */ 99 #define LUNA_MAX_PTSIZE 0x400000 /* max size of UPT */ 100 #define LUNA_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */ 101 #define LUNA_PTBASE 0x10000000 /* UPT map base address */ 102 #define LUNA_PTMAXSIZE 0x20000000 /* UPT map maximum size */ 103 104 /* 105 * Kernel virtual address to page table entry and to physical address. 106 */ 107 #define kvtopte(va) \ 108 (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT]) 109 #define ptetokv(pt) \ 110 ((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS) 111 #define kvtophys(va) \ 112 ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET)) 113 114