1 /* 2 * Copyright (c) 1992 OMRON Corporation. 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * OMRON Corporation. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)sioreg.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* sioreg.h NOV-26-1991 */ 15 16 struct siodevice { 17 volatile u_char sio_data; 18 u_char sio_pad1; 19 volatile u_char sio_cmd; 20 u_char sio_pad2; 21 }; 22 23 #define sio_stat sio_cmd 24 25 #define splsio spl6 26 27 28 #define REG(u, r) ( (u << 4) | r ) 29 #define CHANNEL(r) ( r >> 4 ) 30 #define REGNO(r) ( r & 0x07 ) 31 #define isStatusReg(r) ( r & 0x08 ) 32 33 #define WR0 0x00 34 #define WR1 0x01 35 #define WR2 0x02 36 #define WR3 0x03 37 #define WR4 0x04 38 #define WR5 0x05 39 #define WR6 0x06 40 #define WR7 0x07 41 42 #define WR2A 0x02 43 #define WR2B 0x12 44 45 #define RR0 0x08 46 #define RR1 0x09 47 #define RR2 0x0A 48 #define RR3 0x0B 49 #define RR4 0x0C 50 51 #define RR2A 0x0A 52 #define RR2B 0x1A 53 54 #define WR0_NOP 0x00 /* No Operation */ 55 #define WR0_SNDABRT 0x08 /* Send Abort (HDLC) */ 56 #define WR0_RSTINT 0x10 /* Reset External/Status Interrupt */ 57 #define WR0_CHANRST 0x18 /* Channel Reset */ 58 #define WR0_INTNXT 0x20 /* Enable Interrupt on Next Receive Character */ 59 #define WR0_RSTPEND 0x28 /* Reset Transmitter Interrput/DMA Pending */ 60 #define WR0_ERRRST 0x30 /* Error Reset */ 61 #define WR0_ENDINTR 0x38 /* End of Interrupt */ 62 63 #define WR1_ESENBL 0x01 /* External/Status Interrupt Enable */ 64 #define WR1_TXENBL 0x02 /* Tx Interrupt/DMA Enable */ 65 #define WR1_STATVEC 0x04 /* Status Affects Vector (Only Chan-B) */ 66 #define WR1_RXDSEBL 0x00 /* Rx Interrupt/DMA Disable */ 67 #define WR1_RXFIRST 0x08 /* Interrupt only First Character Received */ 68 #define WR1_RXALLS 0x10 /* Interrupt Every Characters Received (with Special Char.) */ 69 #define WR1_RXALL 0x18 /* Interrupt Every Characters Received (without Special Char.) */ 70 71 #define WR2_INTR_0 0x00 /* Interrupt Priority: RxA TxA RxB TxB E/SA E/SA */ 72 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ 73 #define WR2_VEC85_1 0x00 /* 8085 Vectored Mode - 1 */ 74 #define WR2_VEC85_2 0x08 /* 8085 Vectored Mode - 2 */ 75 #define WR2_VEC86 0x10 /* 8086 Vectored */ 76 #define WR2_VEC85_3 0x18 /* 8085 Vectored Mode - 3 */ 77 78 #define WR3_RXENBL 0x01 /* Rx Enable */ 79 #define WR3_RXCRC 0x08 /* Rx CRC Check */ 80 #define WR3_AUTOEBL 0x20 /* Auto Enable (flow control for MODEM) */ 81 #define WR3_RX5BIT 0x00 /* Rx Bits/Character: 5 Bits */ 82 #define WR3_RX7BIT 0x40 /* Rx Bits/Character: 7 Bits */ 83 #define WR3_RX6BIT 0x80 /* Rx Bits/Character: 6 Bits */ 84 #define WR3_RX8BIT 0xc0 /* Rx Bits/Character: 8 Bits */ 85 86 #define WR4_NPARITY 0x00 /* No Parity */ 87 #define WR4_OPARITY 0x01 /* Parity Odd */ 88 #define WR4_EPARITY 0x02 /* Parity Even */ 89 #define WR4_STOP1 0x04 /* Stop Bits (1bit) */ 90 #define WR4_STOP15 0x08 /* Stop Bits (1.5bit) */ 91 #define WR4_STOP2 0x0c /* Stop Bits (2bit) */ 92 #define WR4_BAUD96 0x40 /* Clock Rate (9600 BAUD) */ 93 #define WR4_BAUD48 0x80 /* Clock Rate (4800 BAUD) */ 94 #define WR4_BAUD24 0xc0 /* Clock Rate (2400 BAUD) */ 95 96 #define WR5_TXCRC 0x01 /* Tx CRC Check */ 97 #define WR5_REQSND 0x02 /* Request To Send (LOW) */ 98 #define WR5_TXENBL 0x08 /* Transmit Enable */ 99 #define WR5_BREAK 0x10 /* Send Break */ 100 #define WR5_TX5BIT 0x00 /* Tx Bits/Character: 5 Bits */ 101 #define WR5_TX7BIT 0x20 /* Tx Bits/Character: 7 Bits */ 102 #define WR5_TX6BIT 0x40 /* Tx Bits/Character: 6 Bits */ 103 #define WR5_TX8BIT 0x60 /* Tx Bits/Character: 8 Bits */ 104 105 #define RR0_RXAVAIL 0x01 /* Rx Character Available */ 106 #define RR0_INTRPEND 0x02 /* Interrupt Pending (Channel-A Only) */ 107 #define RR0_TXEMPTY 0x04 /* Tx Buffer Empty */ 108 #define RR0_BREAK 0x80 /* Break Detected */ 109 110 #define RR1_PARITY 0x10 /* Parity Error */ 111 #define RR1_OVERRUN 0x20 /* Data Over Run */ 112 #define RR1_FRAMING 0x40 /* Framing Error */ 113