xref: /original-bsd/sys/news3400/hbdev/dmac_0448.h (revision 55a00f9d)
12bdf9c61Smckusick /*
2*55a00f9dSbostic  * Copyright (c) 1992, 1993
3*55a00f9dSbostic  *	The Regents of the University of California.  All rights reserved.
42bdf9c61Smckusick  *
52bdf9c61Smckusick  * This code is derived from software contributed to Berkeley by
62bdf9c61Smckusick  * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
72bdf9c61Smckusick  *
82bdf9c61Smckusick  * %sccs.include.redist.c%
92bdf9c61Smckusick  *
102bdf9c61Smckusick  * from: $Hdr: dmac_0448.h,v 4.300 91/06/09 06:21:36 root Rel41 $ SONY
112bdf9c61Smckusick  *
12*55a00f9dSbostic  *	@(#)dmac_0448.h	8.1 (Berkeley) 06/11/93
132bdf9c61Smckusick  */
142bdf9c61Smckusick 
152bdf9c61Smckusick /*
162bdf9c61Smckusick  * Copyright (c) 1989- by SONY Corporation.
172bdf9c61Smckusick  */
182bdf9c61Smckusick /*
192bdf9c61Smckusick  *	dmac_0448.h
202bdf9c61Smckusick  *		DMAC L7A0448
212bdf9c61Smckusick  */
222bdf9c61Smckusick 
232bdf9c61Smckusick /*	dmac register base address	*/
242bdf9c61Smckusick #define DMAC_BASE		0xbfe00000
252bdf9c61Smckusick 
262bdf9c61Smckusick /*	register definition	*/
272bdf9c61Smckusick #define DMAC_GSTAT		(DMAC_BASE + 0xf)
282bdf9c61Smckusick #define DMAC_GSEL		(DMAC_BASE + 0xe)
292bdf9c61Smckusick 
302bdf9c61Smckusick #define DMAC_CSTAT		(DMAC_BASE + 0x2)
312bdf9c61Smckusick #define DMAC_CCTL		(DMAC_BASE + 0x3)
322bdf9c61Smckusick #define DMAC_CTRCL		(DMAC_BASE + 0x4)
332bdf9c61Smckusick #define DMAC_CTRCM		(DMAC_BASE + 0x5)
342bdf9c61Smckusick #define DMAC_CTRCH		(DMAC_BASE + 0x6)
352bdf9c61Smckusick #define DMAC_CTAG		(DMAC_BASE + 0x7)
362bdf9c61Smckusick #define DMAC_CWID		(DMAC_BASE + 0x8)
372bdf9c61Smckusick #define DMAC_COFSL		(DMAC_BASE + 0x9)
382bdf9c61Smckusick #define DMAC_COFSH		(DMAC_BASE + 0xa)
392bdf9c61Smckusick #define DMAC_CMAP		(DMAC_BASE + 0xc)
402bdf9c61Smckusick #define DMAC_CMAPH		(DMAC_BASE + 0xc)
412bdf9c61Smckusick #define DMAC_CMAPL		(DMAC_BASE + 0xd)
422bdf9c61Smckusick 
432bdf9c61Smckusick #ifdef mips
442bdf9c61Smckusick #define	VOLATILE	volatile
452bdf9c61Smckusick #else
462bdf9c61Smckusick #define	VOLATILE
472bdf9c61Smckusick #endif
482bdf9c61Smckusick 
492bdf9c61Smckusick #ifndef U_CHAR
502bdf9c61Smckusick #define U_CHAR	unsigned VOLATILE char
512bdf9c61Smckusick #endif
522bdf9c61Smckusick 
532bdf9c61Smckusick #ifndef U_SHORT
542bdf9c61Smckusick #define U_SHORT	unsigned VOLATILE short
552bdf9c61Smckusick #endif
562bdf9c61Smckusick 
572bdf9c61Smckusick #define dmac_gstat		*(U_CHAR *)DMAC_GSTAT
582bdf9c61Smckusick #define dmac_gsel		*(U_CHAR *)DMAC_GSEL
592bdf9c61Smckusick 
602bdf9c61Smckusick #define dmac_cstat		*(U_CHAR *)DMAC_CSTAT
612bdf9c61Smckusick #define dmac_cctl		*(U_CHAR *)DMAC_CCTL
622bdf9c61Smckusick #define dmac_ctrcl		*(U_CHAR *)DMAC_CTRCL
632bdf9c61Smckusick #define dmac_ctrcm		*(U_CHAR *)DMAC_CTRCM
642bdf9c61Smckusick #define dmac_ctrch		*(U_CHAR *)DMAC_CTRCH
652bdf9c61Smckusick #define dmac_ctag		*(U_CHAR *)DMAC_CTAG
662bdf9c61Smckusick #define dmac_cwid		*(U_CHAR *)DMAC_CWID
672bdf9c61Smckusick #define dmac_cofsl		*(U_CHAR *)DMAC_COFSL
682bdf9c61Smckusick #define dmac_cofsh		*(U_CHAR *)DMAC_COFSH
692bdf9c61Smckusick #define dmac_cmap		*(U_SHORT *)DMAC_CMAP
702bdf9c61Smckusick #define dmac_cmaph		*(U_CHAR *)DMAC_CMAPH
712bdf9c61Smckusick #define dmac_cmapl		*(U_CHAR *)DMAC_CMAPL
722bdf9c61Smckusick 
732bdf9c61Smckusick /*	status/control bit definition	*/
742bdf9c61Smckusick #define	DM_TCZ			0x80
752bdf9c61Smckusick #define	DM_A28			0x40
762bdf9c61Smckusick #define	DM_AFIX			0x20
772bdf9c61Smckusick #define	DM_APAD			0x10
782bdf9c61Smckusick #define	DM_ZINTEN		0x8
792bdf9c61Smckusick #define	DM_RST			0x4
802bdf9c61Smckusick #define	DM_MODE			0x2
812bdf9c61Smckusick #define DM_ENABLE		1
822bdf9c61Smckusick 
832bdf9c61Smckusick /*	general status bit definition	*/
842bdf9c61Smckusick #define CH_INT(x)		(u_char)(1 << (2 * x))
852bdf9c61Smckusick #define CH0_INT			1
862bdf9c61Smckusick #define CH1_INT			4
872bdf9c61Smckusick #define CH2_INT			0x10
882bdf9c61Smckusick #define CH3_INT			0x40
892bdf9c61Smckusick 
902bdf9c61Smckusick #define CH_MRQ(x)		(u_char)(1 << (2 * x + 1))
912bdf9c61Smckusick #define CH0_MRQ			2
922bdf9c61Smckusick #define CH1_MRQ			8
932bdf9c61Smckusick #define CH2_MRQ			0x20
942bdf9c61Smckusick #define CH3_MRQ			0x80
952bdf9c61Smckusick 
962bdf9c61Smckusick /*	channel definition	*/
972bdf9c61Smckusick #define	CH_SCSI			0
982bdf9c61Smckusick #define	CH_FDC			1
992bdf9c61Smckusick #define	CH_AUDIO		2
1002bdf9c61Smckusick #define	CH_VIDEO		3
1012bdf9c61Smckusick 
1022bdf9c61Smckusick /*	dma status		*/
1032bdf9c61Smckusick 
1042bdf9c61Smckusick 	struct	dm_stat {
1052bdf9c61Smckusick 		unsigned int dm_gstat;
1062bdf9c61Smckusick 		unsigned int dm_cstat;
1072bdf9c61Smckusick 		unsigned int dm_cctl;
1082bdf9c61Smckusick 		unsigned int dm_tcnt;
1092bdf9c61Smckusick 		unsigned int dm_offset;
1102bdf9c61Smckusick 		unsigned int dm_tag;
1112bdf9c61Smckusick 		unsigned int dm_width;
1122bdf9c61Smckusick 	} ;
1132bdf9c61Smckusick 
1142bdf9c61Smckusick #define	DMAC_WAIT	nops(10)
1152bdf9c61Smckusick 
1162bdf9c61Smckusick #define PINTEN		0xbfc80001
1172bdf9c61Smckusick # define	DMA_INTEN	0x10
1182bdf9c61Smckusick #define PINTSTAT	0xbfc80003
119