1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: lancereg.h,v 4.300 91/06/09 06:26:05 root Rel41 $ SONY 11 * 12 * @(#)lancereg.h 8.1 (Berkeley) 06/11/93 13 */ 14 15 struct lance { 16 u_short rdp; /* data port */ 17 u_short rap; /* address port */ 18 }; 19 20 /* 21 * Control and status registers 22 */ 23 #define CSR0 0 24 #define CSR1 1 25 #define CSR2 2 26 #define CSR3 3 27 28 /* 29 * CSR0 30 */ 31 #define CSR_ERR 0x8000 /* BABL|CERR|MISS|MERR */ 32 #define CSR_BABL 0x4000 /* transmitter timeout error */ 33 #define CSR_CERR 0x2000 /* collision error */ 34 #define CSR_MISS 0x1000 /* missed packet */ 35 #define CSR_MERR 0x0800 /* memory error */ 36 #define CSR_RINT 0x0400 /* receiver interrupt */ 37 #define CSR_TINT 0x0200 /* transmitter interrupt */ 38 #define CSR_IDON 0x0100 /* initailization done */ 39 #define CSR_INTR 0x0080 /* BABL|MISS|MERR|RINT|TINT|IDON */ 40 #define CSR_INEA 0x0040 /* interrupt enable */ 41 #define CSR_RXON 0x0020 /* receiver on */ 42 #define CSR_TXON 0x0010 /* transmitter on */ 43 #define CSR_TDMD 0x0008 /* transmit demand */ 44 #define CSR_STOP 0x0004 /* disable chip */ 45 #define CSR_STRT 0x0002 /* enable chip */ 46 #define CSR_INIT 0x0001 /* initialize */ 47 48 /* 49 * CSR3 50 */ 51 #define CSR_BSWP 0x0004 /* byte swap */ 52 #define CSR_ACON 0x0002 /* ALE control */ 53 #define CSR_BCON 0x0001 /* byte control */ 54 55 /* 56 * Initialization block 57 */ 58 struct init_block { 59 u_short ib_mode; 60 u_char ib_padr[6]; 61 u_char ib_ladrf[8]; 62 u_short ib_rdra; 63 u_short ib_rlen_rdra; 64 u_short ib_tdra; 65 u_short ib_tlen_tdra; 66 }; 67 68 #define IB_PROM 0x8000 /* promiscuous mode */ 69 #define IB_INTL 0x0040 /* internal loopback */ 70 #define IB_DRTY 0x0020 /* disable retry */ 71 #define IB_COLL 0x0010 /* force collision */ 72 #define IB_DTCR 0x0008 /* disable transmit CRC */ 73 #define IB_LOOP 0x0004 /* loopback */ 74 #define IB_DTX 0x0002 /* disable the transmitter */ 75 #define IB_DRX 0x0001 /* disable the receiver */ 76 77 /* 78 * Descriptor rings 79 */ 80 81 /* 82 * Receive message descriptor 83 */ 84 struct recv_msg_desc { 85 u_short rmd_ladr; 86 u_short rmd_stat; 87 u_short rmd_bcnt; 88 u_short rmd_mcnt; 89 }; 90 91 #define RMD_OWN 0x8000 /* owned by lance */ 92 #define RMD_ERR 0x4000 /* FRAM|OFLO|CRC|BUFF */ 93 #define RMD_FRAM 0x2000 /* framing error */ 94 #define RMD_OFLO 0x1000 /* overflow */ 95 #define RMD_CRC 0x0800 /* CRC error */ 96 #define RMD_BUFF 0x0400 /* buffer error */ 97 #define RMD_STP 0x0200 /* start op packet */ 98 #define RMD_ENP 0x0100 /* end of packet */ 99 #define RMD_HADR 0x00ff /* high order 8 bit of buffer address */ 100 101 /* 102 * Transmit message descriptor 103 */ 104 struct xmit_msg_desc { 105 u_short tmd_ladr; 106 u_short tmd_stat; 107 u_short tmd_bcnt; 108 u_short tmd_error; 109 }; 110 111 #define TMD_OWN 0x8000 /* owned by lance */ 112 #define TMD_ERR 0x4000 /* LCOL|LCAR|UFLO|RTRY */ 113 #define TMD_MORE 0x1000 /* more than one retry */ 114 #define TMD_ONE 0x0800 /* one retry */ 115 #define TMD_DEF 0x0400 /* deferred */ 116 #define TMD_STP 0x0200 /* start of packet */ 117 #define TMD_ENP 0x0100 /* end of packet */ 118 #define TMD_HADR 0x00ff /* high order 8 bit of buffer address */ 119 120 #define TMD_BUFF 0x8000 /* buffer error */ 121 #define TMD_UFLO 0x4000 /* underflow error */ 122 #define TMD_LCOL 0x1000 /* late collision */ 123 #define TMD_LCAR 0x0800 /* loss of carrier */ 124 #define TMD_RTRY 0x0400 /* retry error */ 125 #define TMD_TDR 0x00ff /* time domain refrectometry */ 126