1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY 11 * 12 * @(#)adrsmap.h 7.2 (Berkeley) 12/17/92 13 */ 14 15 /* 16 * adrsmap.h 17 * 18 * Define all hardware address map. 19 */ 20 21 #ifndef __ADRSMAP__ 22 #define __ADRSMAP__ 1 23 24 #include <machine/fix_machine_type.h> 25 26 #ifdef news3400 27 /*---------------------------------------------------------------------- 28 * news3400 29 *----------------------------------------------------------------------*/ 30 /* 31 * timer 32 */ 33 #define RTC_PORT 0xbff407f8 34 #define DATA_PORT 0xbff407f9 35 36 #ifdef notdef 37 #define EN_ITIMER 0xb8000004 /*XXX:???*/ 38 #endif 39 40 #define INTEN0 0xbfc80000 41 #define INTEN0_PERR 0x80 42 #define INTEN0_ABORT 0x40 43 #define INTEN0_BERR 0x20 44 #define INTEN0_TIMINT 0x10 45 #define INTEN0_KBDINT 0x08 46 #define INTEN0_MSINT 0x04 47 #define INTEN0_CFLT 0x02 48 #define INTEN0_CBSY 0x01 49 50 #define INTEN1 0xbfc80001 51 #define INTEN1_BEEP 0x80 52 #define INTEN1_SCC 0x40 53 #define INTEN1_LANCE 0x20 54 #define INTEN1_DMA 0x10 55 #define INTEN1_SLOT1 0x08 56 #define INTEN1_SLOT3 0x04 57 #define INTEN1_EXT1 0x02 58 #define INTEN1_EXT3 0x01 59 60 #define INTST0 0xbfc80002 61 #define INTST0_PERR 0x80 62 #define INTST0_ABORT 0x40 63 #define INTST0_BERR 0x00 /* N/A */ 64 #define INTST0_TIMINT 0x10 65 #define INTST0_KBDINT 0x08 66 #define INTST0_MSINT 0x04 67 #define INTST0_CFLT 0x02 68 #define INTST0_CBSY 0x01 69 #define INTST0_PERR_BIT 7 70 #define INTST0_ABORT_BIT 6 71 #define INTST0_BERR_BIT 5 /* N/A */ 72 #define INTST0_TIMINT_BIT 4 73 #define INTST0_KBDINT_BIT 3 74 #define INTST0_MSINT_BIT 2 75 #define INTST0_CFLT_BIT 1 76 #define INTST0_CBSY_BIT 0 77 78 #define INTST1 0xbfc80003 79 #define INTST1_BEEP 0x80 80 #define INTST1_SCC 0x40 81 #define INTST1_LANCE 0x20 82 #define INTST1_DMA 0x10 83 #define INTST1_SLOT1 0x08 84 #define INTST1_SLOT3 0x04 85 #define INTST1_EXT1 0x02 86 #define INTST1_EXT3 0x01 87 #define INTST1_BEEP_BIT 7 88 #define INTST1_SCC_BIT 6 89 #define INTST1_LANCE_BIT 5 90 #define INTST1_DMA_BIT 4 91 #define INTST1_SLOT1_BIT 3 92 #define INTST1_SLOT3_BIT 2 93 #define INTST1_EXT1_BIT 1 94 #define INTST1_EXT3_BIT 0 95 96 #define INTCLR0 0xbfc80004 97 #define INTCLR0_PERR 0x80 98 #define INTCLR0_ABORT 0x40 99 #define INTCLR0_BERR 0x20 100 #define INTCLR0_TIMINT 0x10 101 #define INTCLR0_KBDINT 0x00 /* N/A */ 102 #define INTCLR0_MSINT 0x00 /* N/A */ 103 #define INTCLR0_CFLT 0x02 104 #define INTCLR0_CBSY 0x01 105 106 #define INTCLR1 0xbfc80005 107 #define INTCLR1_BEEP 0x80 108 #define INTCLR1_SCC 0x00 /* N/A */ 109 #define INTCLR1_LANCE 0x00 /* N/A */ 110 #define INTCLR1_DMA 0x00 /* N/A */ 111 #define INTCLR1_SLOT1 0x00 /* N/A */ 112 #define INTCLR1_SLOT3 0x00 /* N/A */ 113 #define INTCLR1_EXT1 0x00 /* N/A */ 114 #define INTCLR1_EXT3 0x00 /* N/A */ 115 116 #define ITIMER 0xbfc80006 117 #define IOCLOCK 4915200 118 119 #define DIP_SWITCH 0xbfe40000 120 #define IDROM 0xbfe80000 121 122 #define DEBUG_PORT 0xbfcc0003 123 #define DP_READ 0x00 124 #define DP_WRITE 0xf0 125 #define DP_LED0 0x01 126 #define DP_LED1 0x02 127 #define DP_LED2 0x04 128 #define DP_LED3 0x08 129 130 131 #define LANCE_PORT 0xbff80000 132 #define LANCE_MEMORY 0xbffc0000 133 #define ETHER_ID IDROM_PORT 134 135 #define LANCE_PORT1 0xb8c30000 /* expansion lance #1 */ 136 #define LANCE_MEMORY1 0xb8c20000 137 #define ETHER_ID1 0xb8c38000 138 139 #define LANCE_PORT2 0xb8c70000 /* expansion lance #2 */ 140 #define LANCE_MEMORY2 0xb8c60000 141 #define ETHER_ID2 0xb8c78000 142 143 #define IDROM_PORT 0xbfe80000 144 145 #define SCCPORT0B 0xbfec0000 146 #define SCCPORT0A 0xbfec0002 147 #define SCCPORT1B 0xb8c40100 148 #define SCCPORT1A 0xb8c40102 149 #define SCCPORT2B 0xb8c40104 150 #define SCCPORT2A 0xb8c40106 151 #define SCCPORT3B 0xb8c40110 152 #define SCCPORT3A 0xb8c40112 153 #define SCCPORT4B 0xb8c40114 154 #define SCCPORT4A 0xb8c40116 155 156 #define SCC_STATUS0 0xbfcc0002 157 #define SCC_STATUS1 0xb8c40108 158 #define SCC_STATUS2 0xb8c40118 159 160 #define SCCVECT (0x1fcc0007 | MACH_UNCACHED_MEMORY_ADDR) 161 #define SCC_RECV 2 162 #define SCC_XMIT 0 163 #define SCC_CTRL 3 164 #define SCC_STAT 1 165 #define SCC_INT_MASK 0x6 166 167 /*XXX: SHOULD BE FIX*/ 168 #define KEYB_DATA 0xbfd00000 /* keyboard data port */ 169 #define KEYB_STAT 0xbfd00001 /* keyboard status port */ 170 #define KEYB_INTE INTEN0 /* keyboard interrupt enable */ 171 #define KEYB_RESET 0xbfd00002 /* keyboard reset port*/ 172 #define KEYB_INIT1 0xbfd00003 /* keyboard speed */ 173 #define KEYB_INIT2 KEYB_INIT1 /* keyboard clock */ 174 #define KEYB_BUZZ 0xbfd40001 /* keyboard buzzer (length) */ 175 #define KEYB_BUZZF 0xbfd40000 /* keyboard buzzer frequency */ 176 #define MOUSE_DATA 0xbfd00004 /* mouse data port */ 177 #define MOUSE_STAT 0xbfd00005 /* mouse status port */ 178 #define MOUSE_INTE INTEN0 /* mouse interrupt enable */ 179 #define MOUSE_RESET 0xbfd00006 /* mouse reset port */ 180 #define MOUSE_INIT1 0xbfd00007 /* mouse speed */ 181 #define MOUSE_INIT2 MOUSE_INIT1 /* mouse clock */ 182 183 #define RX_MSINTE 0x04 /* Mouse Interrupt Enable */ 184 #define RX_KBINTE 0x08 /* Keyboard Intr. Enable */ 185 #define RX_MSINT 0x04 /* Mouse Interrupted */ 186 #define RX_KBINT 0x08 /* Keyboard Interrupted */ 187 #define RX_MSBUF 0x01 /* Mouse data buffer Full */ 188 #define RX_KBBUF 0x01 /* Keyboard data Full */ 189 #define RX_MSRDY 0x02 /* Mouse data ready */ 190 #define RX_KBRDY 0x02 /* Keyboard data ready */ 191 /*XXX: SHOULD BE FIX*/ 192 193 #define ABEINT_BADDR 0xbfdc0038 194 #endif /* news3400 */ 195 196 #endif /* !__ADRSMAP__ */ 197