1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell, and Kazumasa Utashiro of Software Research 7 * Associates, Inc. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)machConst.h 8.1 (Berkeley) 06/11/93 12 * 13 * machConst.h -- 14 * 15 * Machine dependent constants. 16 * 17 * Copyright (C) 1989 Digital Equipment Corporation. 18 * Permission to use, copy, modify, and distribute this software and 19 * its documentation for any purpose and without fee is hereby granted, 20 * provided that the above copyright notice appears in all copies. 21 * Digital Equipment Corporation makes no representations about the 22 * suitability of this software for any purpose. It is provided "as is" 23 * without express or implied warranty. 24 * 25 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 26 * v 9.2 89/10/21 15:55:22 jhh Exp $ SPRITE (DECWRL) 27 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 28 * v 1.2 89/08/15 18:28:21 rab Exp $ SPRITE (DECWRL) 29 * from: $Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 30 * v 9.1 89/09/18 17:33:00 shirriff Exp $ SPRITE (DECWRL) 31 */ 32 33 #ifndef _MACHCONST 34 #define _MACHCONST 35 36 #define MACH_KUSEG_ADDR 0x0 37 #define MACH_CACHED_MEMORY_ADDR 0x80000000 38 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 39 #define MACH_KSEG2_ADDR 0xc0000000 40 41 #define MACH_CACHED_TO_PHYS(x) MACH_UNMAPPED_TO_PHYS(x) 42 #define MACH_UNCACHED_TO_PHYS(x) MACH_UNMAPPED_TO_PHYS(x) 43 #define MACH_UNMAPPED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 44 45 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 46 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 47 48 #define MACH_CACHED_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 49 #define MACH_UNCACHED_TO_CACHED(x) ((unsigned)(x) & 0x9fffffff) 50 51 #define BETWEEN(x,a,b) ((unsigned)(x) >= (a) && (unsigned)(x) < (b)) 52 53 #define MACH_IS_UNMAPPED(x) \ 54 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 55 #define MACH_IS_CACHED(x) \ 56 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_UNCACHED_MEMORY_ADDR) 57 #define MACH_IS_UNCACHED(x) \ 58 BETWEEN(x, MACH_UNCACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 59 #define MACH_IS_MAPPED(x) \ 60 BETWEEN(x, MACH_CACHED_MEMORY_ADDR, MACH_KSEG2_ADDR) 61 #define MACH_IS_USPACE(x) \ 62 ((unsigned)(x) < MACH_CACHED_MEMORY_ADDR) 63 64 #define MACH_CODE_START 0x80001000 65 #define MACH_RESERVED_ADDR 0xb3000000 /* KU:XXX need this? */ 66 #define MACH_KERNWORK_ADDR 0x800001c0 67 #define MACH_MAXMEMSIZE_ADDR (MACH_KERNWORK_ADDR + 0 * 4) 68 #define MACH_BOOTSW_ADDR (MACH_KERNWORK_ADDR + 1 * 4) 69 #define MACH_BOOTDEV_ADDR (MACH_KERNWORK_ADDR + 2 * 4) 70 #define MACH_HOWTO_ADDR (MACH_KERNWORK_ADDR + 3 * 4) 71 #define MACH_BP_ADDR (MACH_KERNWORK_ADDR + 4 * 4) 72 #define MACH_MONARG_ADDR (MACH_KERNWORK_ADDR + 5 * 4) 73 74 /* 75 * The bits in the cause register. 76 * 77 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 78 * MACH_CR_COP_ERR Coprocessor error. 79 * Interrupt pending bits defined below. 80 * MACH_CR_EXC_CODE The exception type (see exception codes below). 81 */ 82 #define MACH_CR_BR_DELAY 0x80000000 83 #define MACH_CR_COP_ERR 0x30000000 84 #define MACH_CR_EXC_CODE 0x0000003C 85 #define MACH_CR_EXC_CODE_SHIFT 2 86 87 /* 88 * The bits in the status register. All bits are active when set to 1. 89 * 90 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 91 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 92 * MACH_SR_TLB_SHUTDOWN TLB disabled. 93 * MACH_SR_PARITY_ERR Parity error. 94 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 95 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 96 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 97 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 98 * Interrupt enable bits defined below. 99 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 100 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 101 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 102 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 103 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 104 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 105 */ 106 #define MACH_SR_COP_USABILITY 0xf0000000 107 #define MACH_SR_COP_0_BIT 0x10000000 108 #define MACH_SR_COP_1_BIT 0x20000000 109 #define MACH_SR_BOOT_EXC_VEC 0x00400000 110 #define MACH_SR_TLB_SHUTDOWN 0x00200000 111 #define MACH_SR_PARITY_ERR 0x00100000 112 #define MACH_SR_CACHE_MISS 0x00080000 113 #define MACH_SR_PARITY_ZERO 0x00040000 114 #define MACH_SR_SWAP_CACHES 0x00020000 115 #define MACH_SR_ISOL_CACHES 0x00010000 116 #define MACH_SR_KU_OLD 0x00000020 117 #define MACH_SR_INT_ENA_OLD 0x00000010 118 #define MACH_SR_KU_PREV 0x00000008 119 #define MACH_SR_INT_ENA_PREV 0x00000004 120 #define MACH_SR_KU_CUR 0x00000002 121 #define MACH_SR_INT_ENA_CUR 0x00000001 122 #define MACH_SR_MBZ 0x0f8000c0 123 124 /* 125 * The interrupt masks. 126 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 127 */ 128 #define MACH_INT_MASK 0xff00 129 #define MACH_INT_MASK_5 0x8000 130 #define MACH_INT_MASK_4 0x4000 131 #define MACH_INT_MASK_3 0x2000 132 #define MACH_INT_MASK_2 0x1000 133 #define MACH_INT_MASK_1 0x0800 134 #define MACH_INT_MASK_0 0x0400 135 #define MACH_HARD_INT_MASK 0xfc00 136 #define MACH_SOFT_INT_MASK 0x0300 137 #define MACH_SOFT_INT_MASK_1 0x0200 138 #define MACH_SOFT_INT_MASK_0 0x0100 139 140 #define MACH_SPL_MASK_8 0x0000 141 #define MACH_SPL_MASK_7 MACH_SPL_MASK_8 | MACH_INT_MASK_5 142 #define MACH_SPL_MASK_6 MACH_SPL_MASK_7 | MACH_INT_MASK_4 143 #define MACH_SPL_MASK_5 MACH_SPL_MASK_6 | MACH_INT_MASK_3 144 #define MACH_SPL_MASK_4 MACH_SPL_MASK_5 | MACH_INT_MASK_2 145 #define MACH_SPL_MASK_3 MACH_SPL_MASK_4 | MACH_INT_MASK_1 146 #define MACH_SPL_MASK_2 MACH_SPL_MASK_3 | MACH_INT_MASK_0 147 #define MACH_SPL_MASK_1 MACH_SPL_MASK_2 | MACH_SOFT_INT_MASK_1 148 #define MACH_SPL_MASK_0 MACH_SPL_MASK_1 | MACH_SOFT_INT_MASK_0 149 150 /* 151 * The system control status register. 152 */ 153 154 /* 155 * The bits in the context register. 156 */ 157 #define MACH_CNTXT_PTE_BASE 0xFFE00000 158 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 159 160 /* 161 * Location of exception vectors. 162 */ 163 #define MACH_RESET_EXC_VEC 0xBFC00000 164 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 165 #define MACH_GEN_EXC_VEC 0x80000080 166 167 /* 168 * Coprocessor 0 registers: 169 * 170 * MACH_COP_0_TLB_INDEX TLB index. 171 * MACH_COP_0_TLB_RANDOM TLB random. 172 * MACH_COP_0_TLB_LOW TLB entry low. 173 * MACH_COP_0_TLB_CONTEXT TLB context. 174 * MACH_COP_0_BAD_VADDR Bad virtual address. 175 * MACH_COP_0_TLB_HI TLB entry high. 176 * MACH_COP_0_STATUS_REG Status register. 177 * MACH_COP_0_CAUSE_REG Exception cause register. 178 * MACH_COP_0_EXC_PC Exception PC. 179 * MACH_COP_0_PRID Processor revision identifier. 180 */ 181 #define MACH_COP_0_TLB_INDEX $0 182 #define MACH_COP_0_TLB_RANDOM $1 183 #define MACH_COP_0_TLB_LOW $2 184 #define MACH_COP_0_TLB_CONTEXT $4 185 #define MACH_COP_0_BAD_VADDR $8 186 #define MACH_COP_0_TLB_HI $10 187 #define MACH_COP_0_STATUS_REG $12 188 #define MACH_COP_0_CAUSE_REG $13 189 #define MACH_COP_0_EXC_PC $14 190 #define MACH_COP_0_PRID $15 191 192 /* 193 * Values for the code field in a break instruction. 194 */ 195 #define MACH_BREAK_INSTR 0x0000000d 196 #define MACH_BREAK_VAL_MASK 0x03ff0000 197 #define MACH_BREAK_VAL_SHIFT 16 198 #define MACH_BREAK_KDB_VAL 512 199 #define MACH_BREAK_SSTEP_VAL 513 200 #define MACH_BREAK_BRKPT_VAL 514 201 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 202 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 203 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 204 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 205 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 206 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 207 208 /* 209 * Mininum and maximum cache sizes. 210 */ 211 #define MACH_MIN_CACHE_SIZE (16 * 1024) 212 #define MACH_MAX_CACHE_SIZE (256 * 1024) 213 214 /* 215 * The floating point version and status registers. 216 */ 217 #define MACH_FPC_ID $0 218 #define MACH_FPC_CSR $31 219 220 /* 221 * The floating point coprocessor status register bits. 222 */ 223 #define MACH_FPC_ROUNDING_BITS 0x00000003 224 #define MACH_FPC_ROUND_RN 0x00000000 225 #define MACH_FPC_ROUND_RZ 0x00000001 226 #define MACH_FPC_ROUND_RP 0x00000002 227 #define MACH_FPC_ROUND_RM 0x00000003 228 #define MACH_FPC_STICKY_BITS 0x0000007c 229 #define MACH_FPC_STICKY_INEXACT 0x00000004 230 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 231 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 232 #define MACH_FPC_STICKY_DIV0 0x00000020 233 #define MACH_FPC_STICKY_INVALID 0x00000040 234 #define MACH_FPC_ENABLE_BITS 0x00000f80 235 #define MACH_FPC_ENABLE_INEXACT 0x00000080 236 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 237 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 238 #define MACH_FPC_ENABLE_DIV0 0x00000400 239 #define MACH_FPC_ENABLE_INVALID 0x00000800 240 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 241 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 242 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 243 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 244 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 245 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 246 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 247 #define MACH_FPC_COND_BIT 0x00800000 248 #define MACH_FPC_MBZ_BITS 0xff7c0000 249 250 /* 251 * Constants to determine if have a floating point instruction. 252 */ 253 #define MACH_OPCODE_SHIFT 26 254 #define MACH_OPCODE_C1 0x11 255 256 /* 257 * The low part of the TLB entry. 258 */ 259 #define VMMACH_TLB_PF_NUM 0xfffff000 260 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 261 #define VMMACH_TLB_MOD_BIT 0x00000400 262 #define VMMACH_TLB_VALID_BIT 0x00000200 263 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 264 265 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 266 267 /* 268 * The high part of the TLB entry. 269 */ 270 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 271 #define VMMACH_TLB_PID 0x00000fc0 272 #define VMMACH_TLB_PID_SHIFT 6 273 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 274 275 /* 276 * The shift to put the index in the right spot. 277 */ 278 #define VMMACH_TLB_INDEX_SHIFT 8 279 280 /* 281 * The number of TLB entries and the first one that write random hits. 282 */ 283 #define VMMACH_NUM_TLB_ENTRIES 64 284 #define VMMACH_FIRST_RAND_ENTRY 8 285 286 /* 287 * The number of process id entries. 288 */ 289 #define VMMACH_NUM_PIDS 64 290 291 /* 292 * TLB probe return codes. 293 */ 294 #define VMMACH_TLB_NOT_FOUND 0 295 #define VMMACH_TLB_FOUND 1 296 #define VMMACH_TLB_FOUND_WITH_PATCH 2 297 #define VMMACH_TLB_PROBE_ERROR 3 298 299 /* 300 * Kernel virtual address for user page table entries 301 * (i.e., the address for the context register). 302 */ 303 #define VMMACH_PTE_BASE 0xFFC00000 304 305 #endif /* _MACHCONST */ 306