1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: scc.conf,v 4.300 91/06/09 06:44:55 root Rel41 $ SONY 11 * 12 * @(#)scc.conf 8.1 (Berkeley) 06/11/93 13 */ 14 15/* 16 * SCC initialize data 17 */ 18 19#define N_INITDATA sizeof (sccinit_a) 20#define N_SCC 10 21 22char sccinit_a[] = { 23 0x09, 0x80, /* Channel A Reset */ 24 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 25 0x02, SCCVEC0, /* Interrupt Vector */ 26 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 27 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 28 0x06, 0x00, /* Null(No Sync Char) */ 29 0x07, 0x00, /* Null(No Sync Char) */ 30 0x09, 0x01, /* MIE Disable */ 31 0x0a, 0x00, /* NRZ */ 32 0x0b, 0x50, /* Tx & Rx CLK=BPG, TRXC=IN */ 33 0x0c, 0x0e, /* Time Const(L) = 14 (9600) */ 34 0x0d, 0x00, /* Time Const(H) = 0 */ 35 0x0e, 0x02, /* BRG Spc=PCLK, BRG OFF */ 36 0x0e, 0x03, /* BRG ON */ 37 0x03, 0xc1, /* Rx Enable */ 38 0x05, 0xea, /* Tx Enable */ 39 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 40 0x10, 0x10, /* Reset Ext/Status Interrupt(Twice) */ 41 0x09, 0x09, /* MIE */ 42 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 43}; 44 45char sccinit_b[] = { 46 0x09, 0x40, /* Channel B Reset */ 47 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 48 0x02, SCCVEC0, /* Interrupt Vector */ 49 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 50 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 51 0x06, 0x00, /* Null(No Sync Char) */ 52 0x07, 0x00, /* Null(No Sync Char) */ 53 0x09, 0x01, /* MIE Disable */ 54 0x0a, 0x00, /* NRZ */ 55 0x0b, 0x52, /* Tx & Rx, CLK=BRG, TRXC=INP */ 56 0x0c, 0x0e, /* Time Const(L) = 14 (9600) */ 57 0x0d, 0x00, /* Time Const(H) */ 58 0x0e, 0x02, /* BRG, SRC=PCLK, BRG OFF */ 59 0x0e, 0x03, /* BRG ON */ 60 0x03, 0xc1, /* Rx Enable */ 61 0x05, 0xea, /* Tx Enable */ 62 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 63 0x10, 0x10, /* Reset Ext/Status Interrpt(Twice) */ 64 0x09, 0x09, /* MIE */ 65 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 66}; 67 68#if defined(news3400) 69char sccinitxa[] = { 70 0x09, 0x80, /* Channel A Reset */ 71 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 72 0x02, SCCVEC0, /* Interrupt Vector */ 73 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 74 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 75 0x06, 0x00, /* Null(No Sync Char) */ 76 0x07, 0x00, /* Null(No Sync Char) */ 77 0x09, 0x01, /* MIE Disable */ 78 0x0a, 0x00, /* NRZ */ 79 0x0b, 0x50, /* Tx & Rx CLK=BPG, TRXC=IN */ 80 0x0c, 0x0a, /* Time Const(L) = 11 (9600) */ 81 0x0d, 0x00, /* Time Const(H) = 0 */ 82 0x0e, 0x02, /* BRG Spc=PCLK, BRG OFF */ 83 0x0e, 0x03, /* BRG ON */ 84 0x03, 0xc1, /* Rx Enable */ 85 0x05, 0xea, /* Tx Enable */ 86 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 87 0x10, 0x10, /* Reset Ext/Status Interrupt(Twice) */ 88 0x09, 0x09, /* MIE */ 89 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 90}, sccinitxb[] = { 91 0x09, 0x40, /* Channel B Reset */ 92 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 93 0x02, SCCVEC0, /* Interrupt Vector */ 94 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 95 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 96 0x06, 0x00, /* Null(No Sync Char) */ 97 0x07, 0x00, /* Null(No Sync Char) */ 98 0x09, 0x01, /* MIE Disable */ 99 0x0a, 0x00, /* NRZ */ 100 0x0b, 0x52, /* Tx & Rx, CLK=BRG, TRXC=INP */ 101 0x0c, 0x0a, /* Time Const(L)=11 (9600) */ 102 0x0d, 0x00, /* Time Const(H) */ 103 0x0e, 0x02, /* BRG, SRC=PCLK, BRG OFF */ 104 0x0e, 0x03, /* BRG ON */ 105 0x03, 0xc1, /* Rx Enable */ 106 0x05, 0xea, /* Tx Enable */ 107 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 108 0x10, 0x10, /* Reset Ext/Status Interrpt(Twice) */ 109 0x09, 0x09, /* MIE */ 110 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 111}; 112#endif /* news3400 */ 113 114#if defined(news3400) 115Scc_channel sccsw[] = { 116 { /* Remote0 */ 117 0, 118 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 119 (struct scc_reg *)SCCPORT0A, 120 sccinit_a, 121 SCCVEC0, 122 }, 123 { /* Remote1 */ 124 0, 125 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 126 (struct scc_reg *)SCCPORT0B, 127 sccinit_b, 128 SCCVEC0, 129 }, 130 { /* Remote2 */ 131 0, 132 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 133 (struct scc_reg *)SCCPORT1A, 134 sccinitxa, 135 SCCVEC1, 136 }, 137 { /* Remote3 */ 138 0, 139 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 140 (struct scc_reg *)SCCPORT1B, 141 sccinitxb, 142 SCCVEC1, 143 }, 144 { /* Remote4 */ 145 0, 146 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 147 (struct scc_reg *)SCCPORT2A, 148 sccinitxa, 149 SCCVEC2, 150 }, 151 { /* Remote5 */ 152 0, 153 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 154 (struct scc_reg *)SCCPORT2B, 155 sccinitxb, 156 SCCVEC2, 157 }, 158 { /* Remote6 */ 159 0, 160 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 161 (struct scc_reg *)SCCPORT3A, 162 sccinitxa, 163 SCCVEC3, 164 }, 165 { /* Remote7 */ 166 0, 167 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 168 (struct scc_reg *)SCCPORT3B, 169 sccinitxb, 170 SCCVEC3, 171 }, 172 { /* Remote8 */ 173 0, 174 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 175 (struct scc_reg *)SCCPORT4A, 176 sccinitxa, 177 SCCVEC4, 178 }, 179 { /* Remote9 */ 180 0, 181 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 182 (struct scc_reg *)SCCPORT4B, 183 sccinitxb, 184 SCCVEC4, 185 }, 186}; 187#endif /* news3400 */ 188