1/* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: scc.conf,v 4.300 91/06/09 06:44:55 root Rel41 $ SONY 11 * 12 * @(#)scc.conf 7.1 (Berkeley) 06/04/92 13 */ 14 15/* 16 * SCC initialize data 17 */ 18 19#define N_INITDATA sizeof (sccinit_a) 20#define N_SCC 10 21 22#ifdef news700 23char sccinit0b[] = { 24 0x09, 0x40, /* Channel B Reset */ 25 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 26 0x02, SCCVEC0, /* Interrupt Vector */ 27 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 28 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 29 0x06, 0x00, /* Null(No Sync Char) */ 30 0x07, 0x00, /* Null(No Sync Char) */ 31 0x09, 0x01, /* MIE Disable */ 32 0x0a, 0x00, /* NRZ */ 33 0x0b, 0x52, /* Tx & Rx CLK=BPG, TRXC=IN */ 34 0x0c, 0x80, /* Time Const(L) = 128 (1200) */ 35 0x0d, 0x00, /* Time Const(H) = 0 */ 36 0x0e, 0x02, /* BRG Spc=PCLK, BRG OFF */ 37 0x0e, 0x03, /* BRG ON */ 38 0x03, 0xc1, /* Rx Enable */ 39 0x05, 0xea, /* Tx Enable */ 40 0x0f, 0x00, /* All EXT/Status Interrupt Disable */ 41 0x10, 0x10, /* Reset Ext/Status Interrupt(Twice) */ 42 0x09, 0x09, /* MIE */ 43 0x01, 0x10 /* Rx Interrupt Enable */ 44}; 45#endif /* news 700 */ 46 47char sccinit_a[] = { 48 0x09, 0x80, /* Channel A Reset */ 49 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 50 0x02, SCCVEC0, /* Interrupt Vector */ 51 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 52 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 53 0x06, 0x00, /* Null(No Sync Char) */ 54 0x07, 0x00, /* Null(No Sync Char) */ 55 0x09, 0x01, /* MIE Disable */ 56 0x0a, 0x00, /* NRZ */ 57 0x0b, 0x50, /* Tx & Rx CLK=BPG, TRXC=IN */ 58#ifdef news1700 59 0x0c, 0x0b, /* Time Const(L) = 11 (9600) */ 60#else /* news1700 */ 61 0x0c, 0x0e, /* Time Const(L) = 14 (9600) */ 62#endif /* news1700 */ 63 0x0d, 0x00, /* Time Const(H) = 0 */ 64 0x0e, 0x02, /* BRG Spc=PCLK, BRG OFF */ 65 0x0e, 0x03, /* BRG ON */ 66 0x03, 0xc1, /* Rx Enable */ 67 0x05, 0xea, /* Tx Enable */ 68 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 69 0x10, 0x10, /* Reset Ext/Status Interrupt(Twice) */ 70 0x09, 0x09, /* MIE */ 71 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 72}; 73 74#ifndef news700 75char sccinit_b[] = { 76 0x09, 0x40, /* Channel B Reset */ 77 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 78 0x02, SCCVEC0, /* Interrupt Vector */ 79 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 80 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 81 0x06, 0x00, /* Null(No Sync Char) */ 82 0x07, 0x00, /* Null(No Sync Char) */ 83 0x09, 0x01, /* MIE Disable */ 84 0x0a, 0x00, /* NRZ */ 85 0x0b, 0x52, /* Tx & Rx, CLK=BRG, TRXC=INP */ 86#ifdef news1700 87 0x0c, 0x0b, /* Time Const(L) = 11 (9600) */ 88#else /* news1700 */ 89 0x0c, 0x0e, /* Time Const(L) = 14 (9600) */ 90#endif /* news1700 */ 91 0x0d, 0x00, /* Time Const(H) */ 92 0x0e, 0x02, /* BRG, SRC=PCLK, BRG OFF */ 93 0x0e, 0x03, /* BRG ON */ 94 0x03, 0xc1, /* Rx Enable */ 95 0x05, 0xea, /* Tx Enable */ 96 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 97 0x10, 0x10, /* Reset Ext/Status Interrpt(Twice) */ 98 0x09, 0x09, /* MIE */ 99 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 100}; 101 102#if defined(news1700) || defined(news3400) 103char sccinitxa[] = { 104 0x09, 0x80, /* Channel A Reset */ 105 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 106 0x02, SCCVEC0, /* Interrupt Vector */ 107 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 108 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 109 0x06, 0x00, /* Null(No Sync Char) */ 110 0x07, 0x00, /* Null(No Sync Char) */ 111 0x09, 0x01, /* MIE Disable */ 112 0x0a, 0x00, /* NRZ */ 113 0x0b, 0x50, /* Tx & Rx CLK=BPG, TRXC=IN */ 114 0x0c, 0x0a, /* Time Const(L) = 11 (9600) */ 115 0x0d, 0x00, /* Time Const(H) = 0 */ 116 0x0e, 0x02, /* BRG Spc=PCLK, BRG OFF */ 117 0x0e, 0x03, /* BRG ON */ 118 0x03, 0xc1, /* Rx Enable */ 119 0x05, 0xea, /* Tx Enable */ 120 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 121 0x10, 0x10, /* Reset Ext/Status Interrupt(Twice) */ 122 0x09, 0x09, /* MIE */ 123 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 124}, sccinitxb[] = { 125 0x09, 0x40, /* Channel B Reset */ 126 0x04, 0x44, /* *16 CLK, 1 Stop Bit, No Parity */ 127 0x02, SCCVEC0, /* Interrupt Vector */ 128 0x03, 0xc0, /* Rx 8bit, Rx Disable */ 129 0x05, 0xe2, /* Tx 8bit, Tx Disable */ 130 0x06, 0x00, /* Null(No Sync Char) */ 131 0x07, 0x00, /* Null(No Sync Char) */ 132 0x09, 0x01, /* MIE Disable */ 133 0x0a, 0x00, /* NRZ */ 134 0x0b, 0x52, /* Tx & Rx, CLK=BRG, TRXC=INP */ 135 0x0c, 0x0a, /* Time Const(L)=11 (9600) */ 136 0x0d, 0x00, /* Time Const(H) */ 137 0x0e, 0x02, /* BRG, SRC=PCLK, BRG OFF */ 138 0x0e, 0x03, /* BRG ON */ 139 0x03, 0xc1, /* Rx Enable */ 140 0x05, 0xea, /* Tx Enable */ 141 0x0f, 0xa8, /* Break, CTS, DCD, Interrupt Enable */ 142 0x10, 0x10, /* Reset Ext/Status Interrpt(Twice) */ 143 0x09, 0x09, /* MIE */ 144 0x01, 0x17 /* Rx Interrupt and Tx Interrupt Enable */ 145}; 146#endif /* news1700 || news3400 */ 147#endif /* !news700 */ 148 149#ifdef news700 150Scc_channel sccsw[] = { 151 { /* Mouse */ 152 0, 153 RXE|TXE|C8BIT|STOP1|RTS|DTR|B1200, 154 (struct scc_reg *)SCCPORT0B, 155 sccinit0b, 156 SCCVEC0, 157 }, 158 { /* keyboard */ 159 0, 160 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 161 (struct scc_reg *)SCCPORT0A, 162 sccinit_a, 163 SCCVEC0, 164 } 165}; 166#endif /* news700 */ 167 168#ifdef news1200 169Scc_channel sccsw[] = { 170 { /* Remote0 */ 171 0, 172 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 173 (struct scc_reg *)SCCPORT0A, 174 sccinit_a, 175 SCCVEC0, 176 }, 177 { /* Remote1 */ 178 0, 179 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 180 (struct scc_reg *)SCCPORT0B, 181 sccinit_b, 182 SCCVEC0, 183 } 184}; 185#endif /* news1200 */ 186 187#if defined(news1700) || defined(news3400) 188Scc_channel sccsw[] = { 189 { /* Remote0 */ 190 0, 191 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 192 (struct scc_reg *)SCCPORT0A, 193 sccinit_a, 194 SCCVEC0, 195 }, 196 { /* Remote1 */ 197 0, 198 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 199 (struct scc_reg *)SCCPORT0B, 200 sccinit_b, 201 SCCVEC0, 202 }, 203 { /* Remote2 */ 204 0, 205 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 206 (struct scc_reg *)SCCPORT1A, 207 sccinitxa, 208 SCCVEC1, 209 }, 210 { /* Remote3 */ 211 0, 212 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 213 (struct scc_reg *)SCCPORT1B, 214 sccinitxb, 215 SCCVEC1, 216 }, 217 { /* Remote4 */ 218 0, 219 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 220 (struct scc_reg *)SCCPORT2A, 221 sccinitxa, 222 SCCVEC2, 223 }, 224 { /* Remote5 */ 225 0, 226 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 227 (struct scc_reg *)SCCPORT2B, 228 sccinitxb, 229 SCCVEC2, 230 }, 231 { /* Remote6 */ 232 0, 233 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 234 (struct scc_reg *)SCCPORT3A, 235 sccinitxa, 236 SCCVEC3, 237 }, 238 { /* Remote7 */ 239 0, 240 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 241 (struct scc_reg *)SCCPORT3B, 242 sccinitxb, 243 SCCVEC3, 244 }, 245 { /* Remote8 */ 246 0, 247 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 248 (struct scc_reg *)SCCPORT4A, 249 sccinitxa, 250 SCCVEC4, 251 }, 252 { /* Remote9 */ 253 0, 254 RXE|TXE|C8BIT|STOP1|RTS|DTR|B9600, 255 (struct scc_reg *)SCCPORT4B, 256 sccinitxb, 257 SCCVEC4, 258 }, 259}; 260#endif /* news1700 || news3400 */ 261