1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc. 7 * 8 * %sccs.include.redist.c% 9 * 10 * from: $Hdr: sccreg.h,v 4.300 91/06/09 06:44:58 root Rel41 $ SONY 11 * 12 * @(#)sccreg.h 8.1 (Berkeley) 06/11/93 13 */ 14 15 #ifndef _SCCREG_ 16 #define _SCCREG_ 17 18 /* 19 * SCC register 20 */ 21 22 struct scc_reg { 23 u_char ctrl; /* control register */ 24 u_char data; /* data register */ 25 }; 26 27 /* 28 * SCC read register 29 */ 30 31 #define RR0 0 32 #define RR1 1 33 #define RR2 2 34 #define RR3 3 35 #define RR10 10 36 #define RR12 12 37 #define RR13 13 38 #define RR15 15 39 40 #define R0_BREAK 0x80 /* Break/Abort */ 41 #define R0_UDRUN 0x40 /* Tx Underrun/EOM */ 42 #define R0_CTS 0x20 /* CTS */ 43 #define R0_SYNC 0x10 /* Sync/Hunt */ 44 #define R0_DCD 0x08 /* DCD */ 45 #define R0_TxBE 0x04 /* Tx buffer empty */ 46 #define R0_ZERO 0x02 /* Zero count */ 47 #define R0_RxCA 0x01 /* Rx char. available */ 48 49 #define R1_EOF 0x80 /* End Of Frame (SDLC) */ 50 #define R1_CRC 0x40 /* CRC/Framing Error */ 51 #define R1_OVRUN 0x20 /* Rx Overrun */ 52 #define R1_PARITY 0x10 /* Parity Error */ 53 #define R1_RESID 0x0e /* Residue code */ 54 #define R1_SENT 0x01 /* All sent */ 55 56 #define R3_RxA 0x20 /* Channel A Rx IP */ 57 #define R3_TxA 0x10 /* Channel A Tx IP */ 58 #define R3_EXTA 0x08 /* Channel A EXT/STAT */ 59 #define R3_RxB 0x20 /* Channel B Rx IP */ 60 #define R3_TxB 0x10 /* Channel B Tx IP */ 61 #define R3_EXTB 0x08 /* Channel B EXT/STAT */ 62 63 #define R10_ONEC 0x80 /* One clock missing */ 64 #define R10_TWOC 0x40 /* Two clock missing */ 65 #define R10_LOOP 0x10 /* Loop Sending */ 66 #define R10_ONLOOP 0x02 /* On Loop */ 67 68 #define R15_BREAK 0x80 /* Break/Abort IE */ 69 #define R15_UDRUN 0x40 /* Tx Underrun IE */ 70 #define R15_CTS 0x20 /* CTS IE */ 71 #define R15_SYNC 0x10 /* Sync/Hunt IE */ 72 #define R15_DCD 0x08 /* DCD IE */ 73 #define R15_ZERO 0x02 /* Zero count IE */ 74 75 /* 76 * SCC write register 77 */ 78 79 #define WR0 0 80 #define WR1 1 81 #define WR2 2 82 #define WR3 3 83 #define WR4 4 84 #define WR5 5 85 #define WR6 6 86 #define WR7 7 87 #define WR9 9 88 #define WR10 10 89 #define WR11 11 90 #define WR12 12 91 #define WR13 13 92 #define WR14 14 93 #define WR15 15 94 95 #define W0_RES_UDRUN 0xc0 /* Reset Tx Underrun/EOM */ 96 #define W0_RES_TxCRC 0x80 /* Reset Tx CRC generator */ 97 #define W0_RES_RxCRC 0x40 /* Reset Rx CRC checker */ 98 #define W0_RES_IUS 0x38 /* Reset Highest IUS */ 99 #define W0_RES_ERROR 0x30 /* Error reset */ 100 #define W0_RES_TxINT 0x28 /* Reset TxINT pending */ 101 #define W0_RxINTE 0x20 /* Enable RxINT on next char. */ 102 #define W0_SND_ABORT 0x18 /* Send Abort (SDLC) */ 103 #define W0_RES_EXT 0x10 /* Reset EXT/STAT interrupts */ 104 105 #define W1_EN_WAIT 0x80 /* WAIT/DMA request enable */ 106 #define W1_WAIT_FUNC 0x40 /* WAIT/DMA request function */ 107 #define W1_WAIT_REQ 0x20 /* WAIT/DMA request on Rx/Tx */ 108 109 #define W1_RxINT_SC 0x18 /* Rx INT on special condition */ 110 #define W1_RxINT_ALL 0x10 /* Rx INT on all character */ 111 #define W1_RxINT_FRST 0x08 /* Rx INT on first character */ 112 #define W1_PARITY 0x04 /* Parity is special condition */ 113 #define W1_TxINTE 0x02 /* Tx INT enable */ 114 #define W1_EXTINTE 0x01 /* EXT INT enable */ 115 116 #define W3_Rx8BIT 0xc0 /* Rx 8 bits/character */ 117 #define W3_Rx6BIT 0x80 /* Rx 6 bits/character */ 118 #define W3_Rx7BIT 0x40 /* Rx 7 bits/character */ 119 #define W3_Rx5BIT 0x00 /* Rx 5 bits/character */ 120 121 #define W3_AUTO 0x20 /* Auto enable */ 122 #define W3_HUNT 0x10 /* Enter Hunt mode */ 123 #define W3_RxCRC 0x08 /* Rx CRC enable */ 124 #define W3_ADDR 0x04 /* Address search mode (SDLC) */ 125 #define W3_SYNCI 0x02 /* Sync char. load inhibit */ 126 #define W3_RxE 0x01 /* Rx enable */ 127 128 #define W4_X64 0xc0 /* X64 clock mode */ 129 #define W4_X32 0x80 /* X32 clock mode */ 130 #define W4_X16 0x40 /* X16 clock mode */ 131 #define W4_X1 0x00 /* X1 clock mode */ 132 133 #define W4_EXTSYNC 0x30 /* External Sync mode */ 134 #define W4_SDLC 0x20 /* SDLC mode */ 135 #define W4_SYNC16 0x10 /* 16 bit sync character */ 136 #define W4_SYNC8 0x00 /* 8 bit sync character */ 137 138 #define W4_STOP2 0x0c /* 2 stop bits/character */ 139 #define W4_STOP1_5 0x08 /* 1.5 stop bits/character */ 140 #define W4_STOP1 0x04 /* 1 stop bit/character */ 141 #define W4_SYNC 0x00 /* Sync mode enable */ 142 143 #define W4_EVEN 0x02 /* Parity Even */ 144 #define W4_PARITY 0x01 /* Parity enable */ 145 146 #define W5_DTR 0x80 /* DTR */ 147 148 #define W5_Tx8BIT 0x60 /* Tx 8 bits/character */ 149 #define W5_Tx6BIT 0x40 /* Tx 6 bits/character */ 150 #define W5_Tx7BIT 0x20 /* Tx 7 bits/character */ 151 #define W5_Tx5BIT 0x00 /* Tx 5 bits/character */ 152 153 #define W5_BREAK 0x10 /* Send Break */ 154 #define W5_TxE 0x08 /* Tx enable */ 155 #define W5_CRC16 0x04 /* SDLC/CRC-16 */ 156 #define W5_RTS 0x02 /* RTS */ 157 #define W5_TxCRC 0x01 /* Tx CRC enable */ 158 159 #define W9_RESET 0xc0 /* Force hardware reset */ 160 #define W9_RES_A 0x80 /* Channel reset A */ 161 #define W9_RES_B 0x40 /* Channel reset B */ 162 163 #define W9_STAT_HIGH 0x10 /* Staus High/Low */ 164 #define W9_MIE 0x08 /* Master Int. enable */ 165 #define W9_DLC 0x04 /* Disable lower chain */ 166 #define W9_NV 0x02 /* Non Vector */ 167 #define W9_VIS 0x01 /* Vector Include Status */ 168 169 #define W10_CRC_PRESET 0x80 /* CRC preset I/O */ 170 171 #define W10_FM0 0x60 /* FM0 (transition = 0) */ 172 #define W10_FM1 0x40 /* FM1 (transition = 1) */ 173 #define W10_NRZI 0x20 /* NRZI */ 174 #define W10_NRZ 0x00 /* NRZ */ 175 176 #define W10_POLL 0x10 /* Go active on poll */ 177 #define W10_MARK 0x08 /* Mark/Flag idle */ 178 #define W10_ABORT 0x04 /* Abort/Flag on underrun */ 179 #define W10_LOOP 0x02 /* Loop mode */ 180 #define W10_SYNC6 0x01 /* 6 bit/8 bit sync */ 181 182 #define W11_RTxC_XTAL 0x80 /* RTxC Xtal */ 183 184 #define W11_RxC_DPLL 0x60 /* RxC = DPLL output */ 185 #define W11_RxC_BRG 0x40 /* RxC = BR Gen. output */ 186 #define W11_RxC_TRxC 0x20 /* RxC = TRxC pin */ 187 #define W11_RxC_RTxC 0x00 /* RxC = RTxC pin */ 188 189 #define W11_TxC_DPLL 0x18 /* TxC = DPLL output */ 190 #define W11_TxC_BRG 0x10 /* TxC = BR Gen. output */ 191 #define W11_TxC_TRxC 0x08 /* TxC = TRxC pin */ 192 #define W11_TxC_RTxC 0x00 /* TxC = RTxC pin */ 193 194 #define W11_TRxC_O 0x04 /* TRxC O/I */ 195 196 #define W11_TRxC_DPLL 0x03 /* TRxC = DPLL output */ 197 #define W11_TRxC_BRG 0x02 /* TRxC = BR Gen output */ 198 #define W11_TRxC_TxC 0x01 /* TRxC = Transmit clock */ 199 #define W11_TRxC_XTAL 0x00 /* TRxC = Xtal output */ 200 201 #define W14_NRZI 0xe0 /* Set NRZI mode */ 202 #define W14_FM 0xc0 /* Set FM mode */ 203 #define W14_RTxC 0xa0 /* Set source = RTxC */ 204 #define W14_BRG 0x80 /* Set source = BR Gen. */ 205 #define W14_DIS_DPLL 0x60 /* Disable DPLL */ 206 #define W14_RES_CLK 0x40 /* Reset missing clock */ 207 #define W14_SEARCH 0x20 /* Enter search mode */ 208 209 #define W14_LOCAL 0x10 /* Local loopback mode */ 210 #define W14_ECHO 0x08 /* Auto echo */ 211 #define W14_DTR 0x04 /* DTR/Request function */ 212 #define W14_BRG_SRC 0x02 /* BR Gen. source */ 213 #define W14_BRGE 0x01 /* BR Gen. enable */ 214 215 #define W15_BREAK 0x80 /* Break/Abort IE */ 216 #define W15_UDRUN 0x40 /* Tx underrun/EOM IE */ 217 #define W15_CTS 0x20 /* CTS IE */ 218 #define W15_SYNC 0x10 /* Sync/Hunt IE */ 219 #define W15_DCD 0x08 /* DCD IE */ 220 #define W15_ZERO 0x02 /* Zero count IE */ 221 222 #endif /* _SCCREG_ */ 223