1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell and Rick Macklem. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)ascreg.h 8.1 (Berkeley) 06/10/93 11 */ 12 13 /* 14 * Mach Operating System 15 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 16 * All Rights Reserved. 17 * 18 * Permission to use, copy, modify and distribute this software and its 19 * documentation is hereby granted, provided that both the copyright 20 * notice and this permission notice appear in all copies of the 21 * software, derivative works or modified versions, and any portions 22 * thereof, and that both notices appear in supporting documentation. 23 * 24 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS 25 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 26 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 27 * 28 * Carnegie Mellon requests users of this software to return to 29 * 30 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 31 * School of Computer Science 32 * Carnegie Mellon University 33 * Pittsburgh PA 15213-3890 34 * 35 * any improvements or extensions that they make and grant Carnegie the 36 * rights to redistribute these changes. 37 */ 38 39 /* 40 * HISTORY 41 * $Log: scsi_53C94.h,v $ 42 * Revision 2.4 91/02/05 17:44:59 mrt 43 * Added author notices 44 * [91/02/04 11:18:32 mrt] 45 * 46 * Changed to use new Mach copyright 47 * [91/02/02 12:17:11 mrt] 48 * 49 * Revision 2.3 90/12/05 23:34:46 af 50 * Documented max DMA xfer size. 51 * [90/12/03 23:39:36 af] 52 * 53 * Revision 2.1.1.1 90/11/01 03:38:54 af 54 * Created, from the DEC specs: 55 * "PMAZ-AA TURBOchannel SCSI Module Functional Specification" 56 * Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990. 57 * And from the NCR data sheets 58 * "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller" 59 * [90/09/03 af] 60 */ 61 62 /* 63 * File: scsi_53C94.h 64 * Author: Alessandro Forin, Carnegie Mellon University 65 * Date: 9/90 66 * 67 * Defines for the NCR 53C94 ASC (SCSI interface) 68 * Some gotcha came from the "86C01/53C94 DMA lab work" written 69 * by Ken Stewart (NCR MED Logic Products Applications Engineer) 70 * courtesy of NCR. Thanks Ken ! 71 */ 72 73 #define ASC_OFFSET_53C94 0x0 /* from module base */ 74 #define ASC_OFFSET_DMAR 0x40000 /* DMA Address Register */ 75 #define ASC_OFFSET_RAM 0x80000 /* SRAM Buffer */ 76 #define ASC_OFFSET_ROM 0xc0000 /* Diagnostic ROM */ 77 78 #define ASC_RAM_SIZE 0x20000 /* 128k (32k*32) */ 79 #define PER_TGT_DMA_SIZE ((ASC_RAM_SIZE/7) & ~(sizeof(int)-1)) 80 #define ASC_NCMD 7 81 82 /* 83 * DMA Address Register 84 */ 85 #define ASC_DMAR_MASK 0x1ffff /* 17 bits, 128k */ 86 #define ASC_DMAR_WRITE 0x80000000 /* DMA direction bit */ 87 #define ASC_DMA_ADDR(x) ((unsigned)(x) & ASC_DMAR_MASK) 88 89 /* 90 * Synch xfer parameters, and timing conversions 91 */ 92 #define SCSI_MIN_PERIOD 50 /* in 4 nsecs units */ 93 #define ASC_MIN_PERIOD25 5 /* in CLKS/BYTE, 1 CLK = 40nsecs */ 94 #define ASC_MIN_PERIOD12 3 /* in CLKS/BYTE, 1 CLK = 80nsecs */ 95 #define ASC_MAX_PERIOD25 35 /* in CLKS/BYTE, 1 CLK = 40nsecs */ 96 #define ASC_MAX_PERIOD12 18 /* in CLKS/BYTE, 1 CLK = 80nsecs */ 97 #define ASC_MAX_OFFSET 15 /* pure number */ 98 /* 99 * Register map, padded as needed 100 */ 101 102 typedef volatile struct { 103 u_char asc_tc_lsb; /* rw: Transfer Counter LSB */ 104 char pad0[3]; 105 u_char asc_tc_msb; /* rw: Transfer Counter MSB */ 106 char pad1[3]; 107 u_char asc_fifo; /* rw: FIFO top */ 108 char pad2[3]; 109 u_char asc_cmd; /* rw: Command */ 110 char pad3[3]; 111 u_char asc_status; /* r: Status */ 112 #define asc_dbus_id asc_status /* w: Destination Bus ID */ 113 char pad4[3]; 114 u_char asc_intr; /* r: Interrupt */ 115 #define asc_sel_timo asc_intr /* w: (re)select timeout */ 116 char pad5[3]; 117 u_char asc_ss; /* r: Sequence Step */ 118 #define asc_syn_p asc_ss /* w: synchronous period */ 119 char pad6[3]; 120 u_char asc_flags; /* r: FIFO flags + seq step */ 121 #define asc_syn_o asc_flags /* w: synchronous offset */ 122 char pad7[3]; 123 u_char asc_cnfg1; /* rw: Configuration 1 */ 124 char pad8[3]; 125 u_char asc_ccf; /* w: Clock Conv. Factor */ 126 char pad9[3]; 127 u_char asc_test; /* w: Test Mode */ 128 char pad10[3]; 129 u_char asc_cnfg2; /* rw: Configuration 2 */ 130 char pad11[3]; 131 u_char asc_cnfg3; /* rw: Configuration 3 */ 132 char pad12[3]; 133 u_char asc_res_fifo; /* w: Reserve FIFO byte */ 134 } asc_regmap_t; 135 136 /* 137 * Transfer Count: access macros 138 * That a NOP is required after loading the dma counter 139 * I learned on the NCR test code. Sic. 140 */ 141 142 #define ASC_TC_MAX 0x10000 143 144 #define ASC_TC_GET(ptr, val) \ 145 val = (ptr)->asc_tc_lsb | ((ptr)->asc_tc_msb << 8) 146 #define ASC_TC_PUT(ptr, val) \ 147 (ptr)->asc_tc_lsb = (val); \ 148 (ptr)->asc_tc_msb = (val) >> 8; \ 149 (ptr)->asc_cmd = ASC_CMD_NOP | ASC_CMD_DMA; 150 151 /* 152 * Command register (command codes) 153 */ 154 155 #define ASC_CMD_DMA 0x80 156 /* Miscellaneous */ 157 #define ASC_CMD_NOP 0x00 158 #define ASC_CMD_FLUSH 0x01 159 #define ASC_CMD_RESET 0x02 160 #define ASC_CMD_BUS_RESET 0x03 161 /* Initiator state */ 162 #define ASC_CMD_XFER_INFO 0x10 163 #define ASC_CMD_I_COMPLETE 0x11 164 #define ASC_CMD_MSG_ACPT 0x12 165 #define ASC_CMD_XFER_PAD 0x18 166 #define ASC_CMD_SET_ATN 0x1a 167 #define ASC_CMD_CLR_ATN 0x1b 168 /* Target state */ 169 #define ASC_CMD_SND_MSG 0x20 170 #define ASC_CMD_SND_STATUS 0x21 171 #define ASC_CMD_SND_DATA 0x22 172 #define ASC_CMD_DISC_SEQ 0x23 173 #define ASC_CMD_TERM 0x24 174 #define ASC_CMD_T_COMPLETE 0x25 175 #define ASC_CMD_DISC 0x27 176 #define ASC_CMD_RCV_MSG 0x28 177 #define ASC_CMD_RCV_CDB 0x29 178 #define ASC_CMD_RCV_DATA 0x2a 179 #define ASC_CMD_RCV_CMD 0x2b 180 #define ASC_CMD_ABRT_DMA 0x04 181 /* Disconnected state */ 182 #define ASC_CMD_RESELECT 0x40 183 #define ASC_CMD_SEL 0x41 184 #define ASC_CMD_SEL_ATN 0x42 185 #define ASC_CMD_SEL_ATN_STOP 0x43 186 #define ASC_CMD_ENABLE_SEL 0x44 187 #define ASC_CMD_DISABLE_SEL 0x45 188 #define ASC_CMD_SEL_ATN3 0x46 189 190 /* 191 * Status register, and phase encoding 192 */ 193 194 #define ASC_CSR_INT 0x80 195 #define ASC_CSR_GE 0x40 196 #define ASC_CSR_PE 0x20 197 #define ASC_CSR_TC 0x10 198 #define ASC_CSR_VGC 0x08 199 #define ASC_CSR_MSG 0x04 200 #define ASC_CSR_CD 0x02 201 #define ASC_CSR_IO 0x01 202 203 #define ASC_PHASE(csr) ((csr) & 0x7) 204 #define ASC_PHASE_DATAO 0x0 205 #define ASC_PHASE_DATAI 0x1 206 #define ASC_PHASE_COMMAND 0x2 207 #define ASC_PHASE_STATUS 0x3 208 /* 4..5 ANSI reserved */ 209 #define ASC_PHASE_MSG_OUT 0x6 210 #define ASC_PHASE_MSG_IN 0x7 211 212 /* 213 * Destination Bus ID 214 */ 215 216 #define ASC_DEST_ID_MASK 0x07 217 218 /* 219 * Interrupt register 220 */ 221 222 #define ASC_INT_RESET 0x80 223 #define ASC_INT_ILL 0x40 224 #define ASC_INT_DISC 0x20 225 #define ASC_INT_BS 0x10 226 #define ASC_INT_FC 0x08 227 #define ASC_INT_RESEL 0x04 228 #define ASC_INT_SEL_ATN 0x02 229 #define ASC_INT_SEL 0x01 230 231 /* 232 * Timeout register: 233 * 234 * val = (timeout * CLK_freq) / (8192 * CCF); 235 */ 236 237 #define ASC_TIMEOUT_250(clk, ccf) (((clk) * 31) / (ccf)) 238 239 /* 240 * Sequence Step register 241 */ 242 243 #define ASC_SS_RESERVED 0xf0 244 #define ASC_SS_SOM 0x08 245 #define ASC_SS_MASK 0x07 246 #define ASC_SS(ss) ((ss) & ASC_SS_MASK) 247 248 /* 249 * Synchronous Transfer Period 250 */ 251 252 #define ASC_STP_MASK 0x1f 253 #define ASC_STP_MIN 0x05 /* 5 clk per byte */ 254 #define ASC_STP_MAX 0x04 /* after ovfl, 35 clk/byte */ 255 256 /* 257 * FIFO flags 258 */ 259 260 #define ASC_FLAGS_SEQ_STEP 0xe0 261 #define ASC_FLAGS_FIFO_CNT 0x1f 262 263 /* 264 * Synchronous offset 265 */ 266 267 #define ASC_SYNO_MASK 0x0f /* 0 -> asyn */ 268 269 /* 270 * Configuration 1 271 */ 272 273 #define ASC_CNFG1_SLOW 0x80 274 #define ASC_CNFG1_SRD 0x40 275 #define ASC_CNFG1_P_TEST 0x20 276 #define ASC_CNFG1_P_CHECK 0x10 277 #define ASC_CNFG1_TEST 0x08 278 #define ASC_CNFG1_MY_BUS_ID 0x07 279 280 /* 281 * CCF register 282 */ 283 284 #define ASC_CCF(clk) ((((clk) - 1) / 5) + 1) 285 286 /* 287 * Test register 288 */ 289 290 #define ASC_TEST_XXXX 0xf8 291 #define ASC_TEST_HI_Z 0x04 292 #define ASC_TEST_I 0x02 293 #define ASC_TEST_T 0x01 294 295 /* 296 * Configuration 2 297 */ 298 299 #define ASC_CNFG2_RFB 0x80 300 #define ASC_CNFG2_EPL 0x40 301 #define ASC_CNFG2_EBC 0x20 302 #define ASC_CNFG2_DREQ_HIZ 0x10 303 #define ASC_CNFG2_SCSI2 0x08 304 #define ASC_CNFG2_BPA 0x04 305 #define ASC_CNFG2_RPE 0x02 306 #define ASC_CNFG2_DPE 0x01 307 308 /* 309 * Configuration 3 310 */ 311 312 #define ASC_CNFG3_RESERVED 0xf8 313 #define ASC_CNFG3_SRB 0x04 314 #define ASC_CNFG3_ALT_DMA 0x02 315 #define ASC_CNFG3_T8 0x01 316