1 /*- 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)ascreg.h 7.1 (Berkeley) 03/09/92 11 */ 12 13 /* 14 * Mach Operating System 15 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 16 * All Rights Reserved. 17 * 18 * Permission to use, copy, modify and distribute this software and its 19 * documentation is hereby granted, provided that both the copyright 20 * notice and this permission notice appear in all copies of the 21 * software, derivative works or modified versions, and any portions 22 * thereof, and that both notices appear in supporting documentation. 23 * 24 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS 25 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 26 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 27 * 28 * Carnegie Mellon requests users of this software to return to 29 * 30 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 31 * School of Computer Science 32 * Carnegie Mellon University 33 * Pittsburgh PA 15213-3890 34 * 35 * any improvements or extensions that they make and grant Carnegie the 36 * rights to redistribute these changes. 37 */ 38 39 /* 40 * HISTORY 41 * $Log: scsi_53C94.h,v $ 42 * Revision 2.4 91/02/05 17:44:59 mrt 43 * Added author notices 44 * [91/02/04 11:18:32 mrt] 45 * 46 * Changed to use new Mach copyright 47 * [91/02/02 12:17:11 mrt] 48 * 49 * Revision 2.3 90/12/05 23:34:46 af 50 * Documented max DMA xfer size. 51 * [90/12/03 23:39:36 af] 52 * 53 * Revision 2.1.1.1 90/11/01 03:38:54 af 54 * Created, from the DEC specs: 55 * "PMAZ-AA TURBOchannel SCSI Module Functional Specification" 56 * Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990. 57 * And from the NCR data sheets 58 * "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller" 59 * [90/09/03 af] 60 */ 61 62 /* 63 * File: scsi_53C94.h 64 * Author: Alessandro Forin, Carnegie Mellon University 65 * Date: 9/90 66 * 67 * Defines for the NCR 53C94 ASC (SCSI interface) 68 * Some gotcha came from the "86C01/53C94 DMA lab work" written 69 * by Ken Stewart (NCR MED Logic Products Applications Engineer) 70 * courtesy of NCR. Thanks Ken ! 71 */ 72 73 /* 74 * Register map, padded as needed 75 */ 76 77 typedef volatile struct { 78 u_char asc_tc_lsb; /* rw: Transfer Counter LSB */ 79 char pad0[3]; 80 u_char asc_tc_msb; /* rw: Transfer Counter MSB */ 81 char pad1[3]; 82 u_char asc_fifo; /* rw: FIFO top */ 83 char pad2[3]; 84 u_char asc_cmd; /* rw: Command */ 85 char pad3[3]; 86 u_char asc_status; /* r: Status */ 87 #define asc_dbus_id asc_status /* w: Destination Bus ID */ 88 char pad4[3]; 89 u_char asc_intr; /* r: Interrupt */ 90 #define asc_sel_timo asc_intr /* w: (re)select timeout */ 91 char pad5[3]; 92 u_char asc_ss; /* r: Sequence Step */ 93 #define asc_syn_p asc_ss /* w: synchronous period */ 94 char pad6[3]; 95 u_char asc_flags; /* r: FIFO flags + seq step */ 96 #define asc_syn_o asc_flags /* w: synchronous offset */ 97 char pad7[3]; 98 u_char asc_cnfg1; /* rw: Configuration 1 */ 99 char pad8[3]; 100 u_char asc_ccf; /* w: Clock Conv. Factor */ 101 char pad9[3]; 102 u_char asc_test; /* w: Test Mode */ 103 char pad10[3]; 104 u_char asc_cnfg2; /* rw: Configuration 2 */ 105 char pad11[3]; 106 u_char asc_cnfg3; /* rw: Configuration 3 */ 107 char pad12[3]; 108 u_char asc_res_fifo; /* w: Reserve FIFO byte */ 109 } asc_regmap_t; 110 111 /* 112 * Transfer Count: access macros 113 * That a NOP is required after loading the dma counter 114 * I learned on the NCR test code. Sic. 115 */ 116 117 #define ASC_TC_MAX 0x10000 118 119 #define ASC_TC_GET(ptr, val) \ 120 val = (ptr)->asc_tc_lsb | ((ptr)->asc_tc_msb << 8) 121 #define ASC_TC_PUT(ptr, val) \ 122 (ptr)->asc_tc_lsb = (val); \ 123 (ptr)->asc_tc_msb = (val) >> 8; \ 124 (ptr)->asc_cmd = ASC_CMD_NOP; 125 126 /* 127 * Command register (command codes) 128 */ 129 130 #define ASC_CMD_DMA 0x80 131 /* Miscellaneous */ 132 #define ASC_CMD_NOP 0x00 133 #define ASC_CMD_FLUSH 0x01 134 #define ASC_CMD_RESET 0x02 135 #define ASC_CMD_BUS_RESET 0x03 136 /* Initiator state */ 137 #define ASC_CMD_XFER_INFO 0x10 138 #define ASC_CMD_I_COMPLETE 0x11 139 #define ASC_CMD_MSG_ACPT 0x12 140 #define ASC_CMD_XFER_PAD 0x18 141 #define ASC_CMD_SET_ATN 0x1a 142 #define ASC_CMD_CLR_ATN 0x1b 143 /* Target state */ 144 #define ASC_CMD_SND_MSG 0x20 145 #define ASC_CMD_SND_STATUS 0x21 146 #define ASC_CMD_SND_DATA 0x22 147 #define ASC_CMD_DISC_SEQ 0x23 148 #define ASC_CMD_TERM 0x24 149 #define ASC_CMD_T_COMPLETE 0x25 150 #define ASC_CMD_DISC 0x27 151 #define ASC_CMD_RCV_MSG 0x28 152 #define ASC_CMD_RCV_CDB 0x29 153 #define ASC_CMD_RCV_DATA 0x2a 154 #define ASC_CMD_RCV_CMD 0x2b 155 #define ASC_CMD_ABRT_DMA 0x04 156 /* Disconnected state */ 157 #define ASC_CMD_RESELECT 0x40 158 #define ASC_CMD_SEL 0x41 159 #define ASC_CMD_SEL_ATN 0x42 160 #define ASC_CMD_SEL_ATN_STOP 0x43 161 #define ASC_CMD_ENABLE_SEL 0x44 162 #define ASC_CMD_DISABLE_SEL 0x45 163 #define ASC_CMD_SEL_ATN3 0x46 164 165 /* 166 * Status register, and phase encoding 167 */ 168 169 #define ASC_CSR_INT 0x80 170 #define ASC_CSR_GE 0x40 171 #define ASC_CSR_PE 0x20 172 #define ASC_CSR_TC 0x10 173 #define ASC_CSR_VGC 0x08 174 #define ASC_CSR_MSG 0x04 175 #define ASC_CSR_CD 0x02 176 #define ASC_CSR_IO 0x01 177 178 #define ASC_PHASE(csr) ((csr) & 0x7) 179 #define ASC_PHASE_DATAO 0x0 180 #define ASC_PHASE_DATAI 0x1 181 #define ASC_PHASE_COMMAND 0x2 182 #define ASC_PHASE_STATUS 0x3 183 /* 4..5 ANSI reserved */ 184 #define ASC_PHASE_MSG_OUT 0x6 185 #define ASC_PHASE_MSG_IN 0x7 186 187 /* 188 * Destination Bus ID 189 */ 190 191 #define ASC_DEST_ID_MASK 0x07 192 193 /* 194 * Interrupt register 195 */ 196 197 #define ASC_INT_RESET 0x80 198 #define ASC_INT_ILL 0x40 199 #define ASC_INT_DISC 0x20 200 #define ASC_INT_BS 0x10 201 #define ASC_INT_FC 0x08 202 #define ASC_INT_RESEL 0x04 203 #define ASC_INT_SEL_ATN 0x02 204 #define ASC_INT_SEL 0x01 205 206 /* 207 * Timeout register: 208 * 209 * val = (timeout * CLK_freq) / (8192 * CCF); 210 */ 211 212 #define ASC_TIMEOUT_250 0x99 /* 250 msecs at 25 Mhz */ 213 214 /* 215 * Sequence Step register 216 */ 217 218 #define ASC_SS_RESERVED 0xf0 219 #define ASC_SS_SOM 0x08 220 #define ASC_SS_MASK 0x07 221 #define ASC_SS(ss) ((ss) & ASC_SS_MASK) 222 223 /* 224 * Synchronous Transfer Period 225 */ 226 227 #define ASC_STP_MASK 0x1f 228 #define ASC_STP_MIN 0x05 /* 5 clk per byte */ 229 #define ASC_STP_MAX 0x04 /* after ovfl, 35 clk/byte */ 230 231 /* 232 * FIFO flags 233 */ 234 235 #define ASC_FLAGS_SEQ_STEP 0xe0 236 #define ASC_FLAGS_FIFO_CNT 0x1f 237 238 /* 239 * Synchronous offset 240 */ 241 242 #define ASC_SYNO_MASK 0x0f /* 0 -> asyn */ 243 244 /* 245 * Configuration 1 246 */ 247 248 #define ASC_CNFG1_SLOW 0x80 249 #define ASC_CNFG1_SRD 0x40 250 #define ASC_CNFG1_P_TEST 0x20 251 #define ASC_CNFG1_P_CHECK 0x10 252 #define ASC_CNFG1_TEST 0x08 253 #define ASC_CNFG1_MY_BUS_ID 0x07 254 255 /* 256 * CCF register 257 */ 258 259 #define ASC_CCF_10MHz 0x2 260 #define ASC_CCF_15MHz 0x3 261 #define ASC_CCF_20MHz 0x4 262 #define ASC_CCF_25MHz 0x5 263 264 /* 265 * Test register 266 */ 267 268 #define ASC_TEST_XXXX 0xf8 269 #define ASC_TEST_HI_Z 0x04 270 #define ASC_TEST_I 0x02 271 #define ASC_TEST_T 0x01 272 273 /* 274 * Configuration 2 275 */ 276 277 #define ASC_CNFG2_RFB 0x80 278 #define ASC_CNFG2_EPL 0x40 279 #define ASC_CNFG2_EBC 0x20 280 #define ASC_CNFG2_DREQ_HIZ 0x10 281 #define ASC_CNFG2_SCSI2 0x08 282 #define ASC_CNFG2_BPA 0x04 283 #define ASC_CNFG2_RPE 0x02 284 #define ASC_CNFG2_DPE 0x01 285 286 /* 287 * Configuration 3 288 */ 289 290 #define ASC_CNFG3_RESERVED 0xf8 291 #define ASC_CNFG3_SRB 0x04 292 #define ASC_CNFG3_ALT_DMA 0x02 293 #define ASC_CNFG3_T8 0x01 294