1 /* 2 * Copyright (c) 1992 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_lereg.h 7.2 (Berkeley) 02/29/92 11 */ 12 13 #define LEMTU 1518 14 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 15 #define LERBUF 32 16 #define LERBUFLOG2 5 17 #define LE_RLEN (LERBUFLOG2 << 13) 18 #define LETBUF 8 19 #define LETBUFLOG2 3 20 #define LE_TLEN (LETBUFLOG2 << 13) 21 22 /* 23 * LANCE registers. 24 */ 25 struct lereg1 { 26 u_short ler1_rdp; /* data port */ 27 short pad0; 28 u_short ler1_rap; /* register select port */ 29 short pad1; 30 }; 31 32 #ifdef DS3100 33 #define LEPAD(x) short x; 34 #define LE_RAM_SIZE 0x10000 35 36 typedef u_short le_buf_t; 37 #endif 38 #ifdef DS5000 39 #define LEPAD(x) 40 #define LE_RAM_SIZE 0x20000 41 42 typedef u_char le_buf_t; 43 #endif 44 45 /* 46 * This structure is overlayed on the network dual-port RAM. 47 * Currently 32 * 1518 receive plus 8 * 1518 transmit buffers plus 48 * buffer descriptor rings. 49 */ 50 struct lereg2 { 51 /* init block */ /* CHIP address */ 52 u_short ler2_mode; /* +0x0000 */ 53 LEPAD(pad0) 54 u_short ler2_padr0; /* +0x0002 */ 55 LEPAD(pad1) 56 u_short ler2_padr1; /* +0x0004 */ 57 LEPAD(pad2) 58 u_short ler2_padr2; /* +0x0006 */ 59 LEPAD(pad3) 60 u_short ler2_ladrf0; /* +0x0008 */ 61 LEPAD(pad4) 62 u_short ler2_ladrf1; /* +0x000A */ 63 LEPAD(pad5) 64 u_short ler2_ladrf2; /* +0x000C */ 65 LEPAD(pad6) 66 u_short ler2_ladrf3; /* +0x000E */ 67 LEPAD(pad7) 68 u_short ler2_rdra; /* +0x0010 */ 69 LEPAD(pad8) 70 u_short ler2_rlen; /* +0x0012 */ 71 LEPAD(pad9) 72 u_short ler2_tdra; /* +0x0014 */ 73 LEPAD(pad10) 74 u_short ler2_tlen; /* +0x0016 */ 75 LEPAD(pad11) 76 /* receive message descriptors */ 77 struct lermd { /* +0x0018 */ 78 u_short rmd0; 79 LEPAD(pad0) 80 u_short rmd1; 81 LEPAD(pad1) 82 short rmd2; 83 LEPAD(pad2) 84 u_short rmd3; 85 LEPAD(pad3) 86 } ler2_rmd[LERBUF]; 87 /* transmit message descriptors */ 88 struct letmd { /* +0x0058 */ 89 u_short tmd0; 90 LEPAD(pad0) 91 u_short tmd1; 92 LEPAD(pad1) 93 short tmd2; 94 LEPAD(pad2) 95 u_short tmd3; 96 LEPAD(pad3) 97 } ler2_tmd[LETBUF]; 98 le_buf_t ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */ 99 le_buf_t ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD0 */ 100 }; 101 102 /* 103 * Control and status bits -- lereg0 104 */ 105 #define LE_IE 0x80 /* interrupt enable */ 106 #define LE_IR 0x40 /* interrupt requested */ 107 #define LE_LOCK 0x08 /* lock status register */ 108 #define LE_ACK 0x04 /* ack of lock */ 109 #define LE_JAB 0x02 /* loss of tx clock (???) */ 110 #define LE_IPL(x) ((((x) >> 4) & 0x3) + 3) 111 112 /* 113 * Control and status bits -- lereg1 114 */ 115 #define LE_CSR0 0 116 #define LE_CSR1 1 117 #define LE_CSR2 2 118 #define LE_CSR3 3 119 120 #define LE_SERR 0x8000 121 #define LE_BABL 0x4000 122 #define LE_CERR 0x2000 123 #define LE_MISS 0x1000 124 #define LE_MERR 0x0800 125 #define LE_RINT 0x0400 126 #define LE_TINT 0x0200 127 #define LE_IDON 0x0100 128 #define LE_INTR 0x0080 129 #define LE_INEA 0x0040 130 #define LE_RXON 0x0020 131 #define LE_TXON 0x0010 132 #define LE_TDMD 0x0008 133 #define LE_STOP 0x0004 134 #define LE_STRT 0x0002 135 #define LE_INIT 0x0001 136 137 #define LE_BSWP 0x4 138 #define LE_MODE 0x0 139 140 /* 141 * Control and status bits -- lereg2 142 */ 143 #define LE_OWN 0x8000 144 #define LE_ERR 0x4000 145 #define LE_STP 0x0200 146 #define LE_ENP 0x0100 147 148 #define LE_FRAM 0x2000 149 #define LE_OFLO 0x1000 150 #define LE_CRC 0x0800 151 #define LE_RBUFF 0x0400 152 153 #define LE_MORE 0x1000 154 #define LE_ONE 0x0800 155 #define LE_DEF 0x0400 156 157 #define LE_TBUFF 0x8000 158 #define LE_UFLO 0x4000 159 #define LE_LCOL 0x1000 160 #define LE_LCAR 0x0800 161 #define LE_RTRY 0x0400 162