1 /* 2 * Copyright (c) 1992 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_lereg.h 7.1 (Berkeley) 01/07/92 11 */ 12 13 #define LEMTU 1518 14 #define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 15 #define LERBUF 32 16 #define LERBUFLOG2 5 17 #define LE_RLEN (LERBUFLOG2 << 13) 18 #define LETBUF 8 19 #define LETBUFLOG2 3 20 #define LE_TLEN (LETBUFLOG2 << 13) 21 22 /* 23 * LANCE registers. 24 */ 25 struct lereg1 { 26 u_short ler1_rdp; /* data port */ 27 short pad0; 28 u_short ler1_rap; /* register select port */ 29 short pad1; 30 }; 31 32 /* 33 * Overlayed on 64Kbyte dual-port RAM. 34 * Currently 32 * 1518 receive plus 8 * 1518 transmit buffers plus 35 * buffer descriptor rings. 36 */ 37 struct lereg2 { 38 /* init block */ /* CHIP address */ 39 u_short ler2_mode; /* +0x0000 */ 40 short pad0; 41 u_short ler2_padr0; /* +0x0002 */ 42 short pad1; 43 u_short ler2_padr1; /* +0x0004 */ 44 short pad2; 45 u_short ler2_padr2; /* +0x0006 */ 46 short pad3; 47 u_short ler2_ladrf0; /* +0x0008 */ 48 short pad4; 49 u_short ler2_ladrf1; /* +0x000A */ 50 short pad5; 51 u_short ler2_ladrf2; /* +0x000C */ 52 short pad6; 53 u_short ler2_ladrf3; /* +0x000E */ 54 short pad7; 55 u_short ler2_rdra; /* +0x0010 */ 56 short pad8; 57 u_short ler2_rlen; /* +0x0012 */ 58 short pad9; 59 u_short ler2_tdra; /* +0x0014 */ 60 short pad10; 61 u_short ler2_tlen; /* +0x0016 */ 62 short pad11; 63 /* receive message descriptors */ 64 struct lermd { /* +0x0018 */ 65 u_short rmd0; 66 short pad0; 67 u_short rmd1; 68 short pad1; 69 short rmd2; 70 short pad2; 71 u_short rmd3; 72 short pad3; 73 } ler2_rmd[LERBUF]; 74 /* transmit message descriptors */ 75 struct letmd { /* +0x0058 */ 76 u_short tmd0; 77 short pad0; 78 u_short tmd1; 79 short pad1; 80 short tmd2; 81 short pad2; 82 u_short tmd3; 83 short pad3; 84 } ler2_tmd[LETBUF]; 85 u_short ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */ 86 u_short ler2_tbuf[LETBUF][LEMTU]; /* +0x2FD0 */ 87 }; 88 89 /* 90 * Control and status bits -- lereg0 91 */ 92 #define LE_IE 0x80 /* interrupt enable */ 93 #define LE_IR 0x40 /* interrupt requested */ 94 #define LE_LOCK 0x08 /* lock status register */ 95 #define LE_ACK 0x04 /* ack of lock */ 96 #define LE_JAB 0x02 /* loss of tx clock (???) */ 97 #define LE_IPL(x) ((((x) >> 4) & 0x3) + 3) 98 99 /* 100 * Control and status bits -- lereg1 101 */ 102 #define LE_CSR0 0 103 #define LE_CSR1 1 104 #define LE_CSR2 2 105 #define LE_CSR3 3 106 107 #define LE_SERR 0x8000 108 #define LE_BABL 0x4000 109 #define LE_CERR 0x2000 110 #define LE_MISS 0x1000 111 #define LE_MERR 0x0800 112 #define LE_RINT 0x0400 113 #define LE_TINT 0x0200 114 #define LE_IDON 0x0100 115 #define LE_INTR 0x0080 116 #define LE_INEA 0x0040 117 #define LE_RXON 0x0020 118 #define LE_TXON 0x0010 119 #define LE_TDMD 0x0008 120 #define LE_STOP 0x0004 121 #define LE_STRT 0x0002 122 #define LE_INIT 0x0001 123 124 #define LE_BSWP 0x4 125 #define LE_MODE 0x0 126 127 /* 128 * Control and status bits -- lereg2 129 */ 130 #define LE_OWN 0x8000 131 #define LE_ERR 0x4000 132 #define LE_STP 0x0200 133 #define LE_ENP 0x0100 134 135 #define LE_FRAM 0x2000 136 #define LE_OFLO 0x1000 137 #define LE_CRC 0x0800 138 #define LE_RBUFF 0x0400 139 140 #define LE_MORE 0x1000 141 #define LE_ONE 0x0800 142 #define LE_DEF 0x0400 143 144 #define LE_TBUFF 0x8000 145 #define LE_UFLO 0x4000 146 #define LE_LCOL 0x1000 147 #define LE_LCAR 0x0800 148 #define LE_RTRY 0x0400 149