1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell and Rick Macklem. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)xcfbreg.h 8.1 (Berkeley) 06/10/93 11 */ 12 13 /* 14 * Mach Operating System 15 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 16 * All Rights Reserved. 17 * 18 * Permission to use, copy, modify and distribute this software and its 19 * documentation is hereby granted, provided that both the copyright 20 * notice and this permission notice appear in all copies of the 21 * software, derivative works or modified versions, and any portions 22 * thereof, and that both notices appear in supporting documentation. 23 * 24 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 25 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 26 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 27 * 28 * Carnegie Mellon requests users of this software to return to 29 * 30 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 31 * School of Computer Science 32 * Carnegie Mellon University 33 * Pittsburgh PA 15213-3890 34 * 35 * any improvements or extensions that they make and grant Carnegie Mellon 36 * the rights to redistribute these changes. 37 */ 38 /* 39 * Defines for the Inmos IMS-G332 Colour video controller 40 * Author: Alessandro Forin, Carnegie Mellon University 41 * See: IMS G332 Colour Video Controller, 1990 Databook, pg 139-163, 42 * Inmos, Ltd. 43 */ 44 45 #define IMS332_ADDRESS 0xbc140000 46 #define VRAM_OFFSET 0x2000000 47 #define IMS332_RESET_ADDRESS 0xbc040100 48 49 /* 50 * Although the chip is built to be memory-mapped 51 * it can be programmed for 32 or 64 bit addressing. 52 * Moreover, the hardware bits have been twisted 53 * even more on the machine I am writing this for. 54 * So I'll just define the chip's offsets and leave 55 * it to the implementation to define the rest. 56 */ 57 #define IMS332_REG_BOOT 0x000 /* boot time config */ 58 59 #define IMS332_REG_HALF_SYNCH 0x021 /* datapath registers */ 60 #define IMS332_REG_BACK_PORCH 0x022 61 #define IMS332_REG_DISPLAY 0x023 62 #define IMS332_REG_SHORT_DIS 0x024 63 #define IMS332_REG_BROAD_PULSE 0x025 64 #define IMS332_REG_V_SYNC 0x026 65 #define IMS332_REG_V_PRE_EQUALIZE 0x027 66 #define IMS332_REG_V_POST_EQUALIZE 0x028 67 #define IMS332_REG_V_BLANK 0x029 68 #define IMS332_REG_V_DISPLAY 0x02a 69 #define IMS332_REG_LINE_TIME 0x02b 70 #define IMS332_REG_LINE_START 0x02c 71 #define IMS332_REG_MEM_INIT 0x02d 72 #define IMS332_REG_XFER_DELAY 0x02e 73 74 #define IMS332_REG_COLOR_MASK 0x040 /* color mask register */ 75 76 #define IMS332_REG_CSR_A 0x060 77 78 #define IMS332_REG_CSR_B 0x070 79 80 #define IMS332_REG_TOP_SCREEN 0x080 /* top-of-screen offset */ 81 82 #define IMS332_REG_CURSOR_LUT_0 0x0a1 /* cursor palette */ 83 #define IMS332_REG_CURSOR_LUT_1 0x0a2 84 #define IMS332_REG_CURSOR_LUT_2 0x0a3 85 86 #define IMS332_REG_RGB_CKSUM_0 0x0c0 /* test registers */ 87 #define IMS332_REG_RGB_CKSUM_1 0x0c1 88 #define IMS332_REG_RGB_CKSUM_2 0x0c2 89 90 #define IMS332_REG_CURSOR_LOC 0x0c7 /* cursor location */ 91 92 #define IMS332_REG_LUT_BASE 0x100 /* color palette */ 93 #define IMS332_REG_LUT_END 0x1ff 94 95 #define IMS332_REG_CURSOR_RAM 0x200 /* cursor bitmap */ 96 #define IMS332_REG_CURSOR_RAM_END 0x3ff 97 98 /* 99 * Control register A 100 */ 101 102 #define IMS332_CSR_A_VTG_ENABLE 0x000001 /* vertical timing generator */ 103 #define IMS332_CSR_A_INTERLACED 0x000002 /* screen format */ 104 #define IMS332_CSR_A_CCIR 0x000004 /* default is EIA */ 105 #define IMS332_CSR_A_SLAVE_SYNC 0x000008 /* else from our pll */ 106 #define IMS332_CSR_A_PLAIN_SYNC 0x000010 /* else tesselated */ 107 #define IMS332_CSR_A_SEPARATE_SYNC 0x000020 /* else composite */ 108 #define IMS332_CSR_A_VIDEO_ONLY 0x000040 /* else video+sync */ 109 #define IMS332_CSR_A_BLANK_PEDESTAL 0x000080 /* blank level */ 110 #define IMS332_CSR_A_CBLANK_IS_OUT 0x000100 111 #define IMS332_CSR_A_CBLANK_NO_DELAY 0x000200 112 #define IMS332_CSR_A_FORCE_BLANK 0x000400 113 #define IMS332_CSR_A_BLANK_DISABLE 0x000800 114 #define IMS332_CSR_A_VRAM_INCREMENT 0x003000 115 # define IMS332_VRAM_INC_1 0x000000 116 # define IMS332_VRAM_INC_256 0x001000 /* except interlaced->2 */ 117 # define IMS332_VRAM_INC_512 0x002000 118 # define IMS332_VRAM_INC_1024 0x003000 119 #define IMS332_CSR_A_DMA_DISABLE 0x004000 120 #define IMS332_CSR_A_SYNC_DELAY_MASK 0x038000 /* 0-7 VTG clk delays */ 121 #define IMS332_CSR_A_PIXEL_INTERLEAVE 0x040000 122 #define IMS332_CSR_A_DELAYED_SAMPLING 0x080000 123 #define IMS332_CSR_A_BITS_PER_PIXEL 0x700000 124 # define IMS332_BPP_1 0x000000 125 # define IMS332_BPP_2 0x100000 126 # define IMS332_BPP_4 0x200000 127 # define IMS332_BPP_8 0x300000 128 # define IMS332_BPP_15 0x400000 129 # define IMS332_BPP_16 0x500000 130 #define IMS332_CSR_A_DISABLE_CURSOR 0x800000 131 132 133 /* 134 * Control register B is mbz 135 */ 136 137 /* 138 * Boot register 139 */ 140 141 #define IMS332_BOOT_PLL 0x00001f /* xPLL, binary */ 142 #define IMS332_BOOT_CLOCK_PLL 0x000020 /* else xternal */ 143 #define IMS332_BOOT_64_BIT_MODE 0x000040 /* else 32 */ 144 #define IMS332_BOOT_xxx 0xffff80 /* reserved, mbz */ 145