1 /* 2 * Copyright (c) 1992 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)machConst.h 7.2 (Berkeley) 02/29/92 11 * 12 * machConst.h -- 13 * 14 * Machine dependent constants. 15 * 16 * Copyright (C) 1989 Digital Equipment Corporation. 17 * Permission to use, copy, modify, and distribute this software and 18 * its documentation for any purpose and without fee is hereby granted, 19 * provided that the above copyright notice appears in all copies. 20 * Digital Equipment Corporation makes no representations about the 21 * suitability of this software for any purpose. It is provided "as is" 22 * without express or implied warranty. 23 * 24 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 25 * v 9.2 89/10/21 15:55:22 jhh Exp $ SPRITE (DECWRL) 26 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 27 * v 1.2 89/08/15 18:28:21 rab Exp $ SPRITE (DECWRL) 28 * from: $Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 29 * v 9.1 89/09/18 17:33:00 shirriff Exp $ SPRITE (DECWRL) 30 */ 31 32 #ifndef _MACHCONST 33 #define _MACHCONST 34 35 #define MACH_KUSEG_ADDR 0x0 36 #define MACH_CACHED_MEMORY_ADDR 0x80000000 37 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 38 #define MACH_KSEG2_ADDR 0xc0000000 39 40 #define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 41 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 42 #define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 43 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 44 45 #ifdef DS3100 46 #define MACH_MAX_MEM_ADDR 0xa1800000 47 #define MACH_CACHED_FRAME_BUFFER_ADDR 0x8fc00000 48 #define MACH_UNCACHED_FRAME_BUFFER_ADDR 0xafc00000 49 #define MACH_PLANE_MASK_ADDR 0xb0000000 50 #define MACH_CURSOR_REG_ADDR 0xb1000000 51 #define MACH_COLOR_MAP_ADDR 0xb2000000 52 #define MACH_RESERVED_ADDR 0xb3000000 53 #define MACH_WRITE_ERROR_ADDR 0xb7000000 54 #define MACH_NETWORK_INTERFACE_ADDR 0xb8000000 55 #define MACH_NETWORK_BUFFER_ADDR 0xb9000000 56 #define MACH_SCSI_INTERFACE_ADDR 0xba000000 57 #define MACH_SCSI_BUFFER_ADDR 0xbb000000 58 #define MACH_SERIAL_INTERFACE_ADDR 0xbc000000 59 #define MACH_CLOCK_ADDR 0xbd000000 60 #define MACH_SYS_CSR_ADDR 0xbe000000 61 #endif 62 63 #ifdef DS5000 64 #define MACH_MAX_MEM_ADDR 0xbe000000 65 #define MACH_RESERVED_ADDR 0xbfc80000 66 #define MACH_CHKSYN_ADDR 0xbfd00000 67 #define MACH_ERROR_ADDR 0xbfd80000 68 #define MACH_SERIAL_INTERFACE_ADDR 0xbfe00000 69 #define MACH_CLOCK_ADDR 0xbfe80000 70 #define MACH_SYS_CSR_ADDR 0xbff00000 71 #endif 72 73 #define MACH_CODE_START 0x80030000 74 75 /* 76 * The bits in the cause register. 77 * 78 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 79 * MACH_CR_COP_ERR Coprocessor error. 80 * Interrupt pending bits defined below. 81 * MACH_CR_EXC_CODE The exception type (see exception codes below). 82 */ 83 #define MACH_CR_BR_DELAY 0x80000000 84 #define MACH_CR_COP_ERR 0x30000000 85 #define MACH_CR_EXC_CODE 0x0000003C 86 #define MACH_CR_EXC_CODE_SHIFT 2 87 88 /* 89 * The bits in the status register. All bits are active when set to 1. 90 * 91 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 92 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 93 * MACH_SR_TLB_SHUTDOWN TLB disabled. 94 * MACH_SR_PARITY_ERR Parity error. 95 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 96 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 97 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 98 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 99 * Interrupt enable bits defined below. 100 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 101 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 102 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 103 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 104 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 105 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 106 */ 107 #define MACH_SR_COP_USABILITY 0xf0000000 108 #define MACH_SR_COP_0_BIT 0x10000000 109 #define MACH_SR_COP_1_BIT 0x20000000 110 #define MACH_SR_BOOT_EXC_VEC 0x00400000 111 #define MACH_SR_TLB_SHUTDOWN 0x00200000 112 #define MACH_SR_PARITY_ERR 0x00100000 113 #define MACH_SR_CACHE_MISS 0x00080000 114 #define MACH_SR_PARITY_ZERO 0x00040000 115 #define MACH_SR_SWAP_CACHES 0x00020000 116 #define MACH_SR_ISOL_CACHES 0x00010000 117 #define MACH_SR_KU_OLD 0x00000020 118 #define MACH_SR_INT_ENA_OLD 0x00000010 119 #define MACH_SR_KU_PREV 0x00000008 120 #define MACH_SR_INT_ENA_PREV 0x00000004 121 #define MACH_SR_KU_CUR 0x00000002 122 #define MACH_SR_INT_ENA_CUR 0x00000001 123 #define MACH_SR_MBZ 0x0f8000c0 124 125 /* 126 * The interrupt masks. 127 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 128 */ 129 #define MACH_INT_MASK 0xff00 130 #define MACH_INT_MASK_5 0x8000 131 #define MACH_INT_MASK_4 0x4000 132 #define MACH_INT_MASK_3 0x2000 133 #define MACH_INT_MASK_2 0x1000 134 #define MACH_INT_MASK_1 0x0800 135 #define MACH_INT_MASK_0 0x0400 136 #define MACH_HARD_INT_MASK 0xfc00 137 #define MACH_SOFT_INT_MASK_1 0x0200 138 #define MACH_SOFT_INT_MASK_0 0x0100 139 140 /* 141 * The system control status register. 142 */ 143 #ifdef DS3100 144 #define MACH_CSR_MONO 0x0800 145 #define MACH_CSR_MEM_ERR 0x0400 146 #define MACH_CSR_VINT 0x0200 147 #define MACH_CSR_MBZ 0x9800 148 #endif 149 150 #ifdef DS5000 151 #define MACH_CSR_IOINT_MASK 0x000000FF 152 #define MACH_CSR_BAUD38 0x00000100 153 #define MACH_CSR_DIAGDN 0x00000200 154 #define MACH_CSR_BNK32M 0x00000400 155 #define MACH_CSR_TXDIS 0x00000800 156 #define MACH_CSR_LEDIAG 0x00001000 157 #define MACH_CSR_CORRECT 0x00002000 158 #define MACH_CSR_ECCMD 0x0000C000 159 #define MACH_CSR_IOINTEN_MASK 0x00FF0000 160 #define MACH_CSR_IOINTEN_SHIFT 16 161 #define MACH_CSR_NRMMOD 0x01000000 162 #define MACH_CSR_REFEVEN 0x02000000 163 #define MACH_CSR_PRSVNVR 0x04000000 164 #define MACH_CSR_PSWARN 0x08000000 165 #define MACH_CSR_MBZ 0xFF000000 166 #endif 167 168 /* 169 * The bits in the context register. 170 */ 171 #define MACH_CNTXT_PTE_BASE 0xFFE00000 172 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 173 174 /* 175 * Location of exception vectors. 176 */ 177 #define MACH_RESET_EXC_VEC 0xBFC00000 178 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 179 #define MACH_GEN_EXC_VEC 0x80000080 180 181 /* 182 * Coprocessor 0 registers: 183 * 184 * MACH_COP_0_TLB_INDEX TLB index. 185 * MACH_COP_0_TLB_RANDOM TLB random. 186 * MACH_COP_0_TLB_LOW TLB entry low. 187 * MACH_COP_0_TLB_CONTEXT TLB context. 188 * MACH_COP_0_BAD_VADDR Bad virtual address. 189 * MACH_COP_0_TLB_HI TLB entry high. 190 * MACH_COP_0_STATUS_REG Status register. 191 * MACH_COP_0_CAUSE_REG Exception cause register. 192 * MACH_COP_0_EXC_PC Exception PC. 193 * MACH_COP_0_PRID Processor revision identifier. 194 */ 195 #define MACH_COP_0_TLB_INDEX $0 196 #define MACH_COP_0_TLB_RANDOM $1 197 #define MACH_COP_0_TLB_LOW $2 198 #define MACH_COP_0_TLB_CONTEXT $4 199 #define MACH_COP_0_BAD_VADDR $8 200 #define MACH_COP_0_TLB_HI $10 201 #define MACH_COP_0_STATUS_REG $12 202 #define MACH_COP_0_CAUSE_REG $13 203 #define MACH_COP_0_EXC_PC $14 204 #define MACH_COP_0_PRID $15 205 206 /* 207 * Values for the code field in a break instruction. 208 */ 209 #define MACH_BREAK_INSTR 0x0000000d 210 #define MACH_BREAK_VAL_MASK 0x03ff0000 211 #define MACH_BREAK_VAL_SHIFT 16 212 #define MACH_BREAK_KDB_VAL 512 213 #define MACH_BREAK_SSTEP_VAL 513 214 #define MACH_BREAK_BRKPT_VAL 514 215 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 216 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 217 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 218 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 219 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 220 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 221 222 /* 223 * Mininum and maximum cache sizes. 224 */ 225 #define MACH_MIN_CACHE_SIZE (16 * 1024) 226 #define MACH_MAX_CACHE_SIZE (256 * 1024) 227 228 /* 229 * The floating point version and status registers. 230 */ 231 #define MACH_FPC_ID $0 232 #define MACH_FPC_CSR $31 233 234 /* 235 * The floating point coprocessor status register bits. 236 */ 237 #define MACH_FPC_ROUNDING_BITS 0x00000003 238 #define MACH_FPC_ROUND_RN 0x00000000 239 #define MACH_FPC_ROUND_RZ 0x00000001 240 #define MACH_FPC_ROUND_RP 0x00000002 241 #define MACH_FPC_ROUND_RM 0x00000003 242 #define MACH_FPC_STICKY_BITS 0x0000007c 243 #define MACH_FPC_STICKY_INEXACT 0x00000004 244 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 245 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 246 #define MACH_FPC_STICKY_DIV0 0x00000020 247 #define MACH_FPC_STICKY_INVALID 0x00000040 248 #define MACH_FPC_ENABLE_BITS 0x00000f80 249 #define MACH_FPC_ENABLE_INEXACT 0x00000080 250 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 251 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 252 #define MACH_FPC_ENABLE_DIV0 0x00000400 253 #define MACH_FPC_ENABLE_INVALID 0x00000800 254 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 255 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 256 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 257 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 258 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 259 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 260 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 261 #define MACH_FPC_COND_BIT 0x00800000 262 #define MACH_FPC_MBZ_BITS 0xff7c0000 263 264 /* 265 * Constants to determine if have a floating point instruction. 266 */ 267 #define MACH_OPCODE_SHIFT 26 268 #define MACH_OPCODE_C1 0x11 269 270 /* 271 * The low part of the TLB entry. 272 */ 273 #define VMMACH_TLB_PF_NUM 0xfffff000 274 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 275 #define VMMACH_TLB_MOD_BIT 0x00000400 276 #define VMMACH_TLB_VALID_BIT 0x00000200 277 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 278 279 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 280 281 /* 282 * The high part of the TLB entry. 283 */ 284 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 285 #define VMMACH_TLB_PID 0x00000fc0 286 #define VMMACH_TLB_PID_SHIFT 6 287 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 288 289 /* 290 * The shift to put the index in the right spot. 291 */ 292 #define VMMACH_TLB_INDEX_SHIFT 8 293 294 /* 295 * The number of TLB entries and the first one that write random hits. 296 */ 297 #define VMMACH_NUM_TLB_ENTRIES 64 298 #define VMMACH_FIRST_RAND_ENTRY 8 299 300 /* 301 * The number of process id entries. 302 */ 303 #define VMMACH_NUM_PIDS 64 304 305 /* 306 * TLB probe return codes. 307 */ 308 #define VMMACH_TLB_NOT_FOUND 0 309 #define VMMACH_TLB_FOUND 1 310 #define VMMACH_TLB_FOUND_WITH_PATCH 2 311 #define VMMACH_TLB_PROBE_ERROR 3 312 313 /* 314 * Kernel virtual address for user page table entries 315 * (i.e., the address for the context register). 316 */ 317 #define VMMACH_PTE_BASE 0xFFC00000 318 319 #endif /* _MACHCONST */ 320