1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell and Rick Macklem. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)machConst.h 7.3 (Berkeley) 11/15/92 11 * 12 * machConst.h -- 13 * 14 * Machine dependent constants. 15 * 16 * Copyright (C) 1989 Digital Equipment Corporation. 17 * Permission to use, copy, modify, and distribute this software and 18 * its documentation for any purpose and without fee is hereby granted, 19 * provided that the above copyright notice appears in all copies. 20 * Digital Equipment Corporation makes no representations about the 21 * suitability of this software for any purpose. It is provided "as is" 22 * without express or implied warranty. 23 * 24 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 25 * v 9.2 89/10/21 15:55:22 jhh Exp $ SPRITE (DECWRL) 26 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 27 * v 1.2 89/08/15 18:28:21 rab Exp $ SPRITE (DECWRL) 28 * from: $Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 29 * v 9.1 89/09/18 17:33:00 shirriff Exp $ SPRITE (DECWRL) 30 */ 31 32 #ifndef _MACHCONST 33 #define _MACHCONST 34 35 #define MACH_KUSEG_ADDR 0x0 36 #define MACH_CACHED_MEMORY_ADDR 0x80000000 37 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 38 #define MACH_KSEG2_ADDR 0xc0000000 39 #define MACH_MAX_MEM_ADDR 0xbe000000 40 #define MACH_RESERVED_ADDR 0xbfc80000 41 42 #define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 43 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 44 #define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 45 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 46 47 #define MACH_CODE_START 0x80030000 48 49 /* 50 * The bits in the cause register. 51 * 52 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 53 * MACH_CR_COP_ERR Coprocessor error. 54 * Interrupt pending bits defined below. 55 * MACH_CR_EXC_CODE The exception type (see exception codes below). 56 */ 57 #define MACH_CR_BR_DELAY 0x80000000 58 #define MACH_CR_COP_ERR 0x30000000 59 #define MACH_CR_EXC_CODE 0x0000003C 60 #define MACH_CR_EXC_CODE_SHIFT 2 61 62 /* 63 * The bits in the status register. All bits are active when set to 1. 64 * 65 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 66 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 67 * MACH_SR_TLB_SHUTDOWN TLB disabled. 68 * MACH_SR_PARITY_ERR Parity error. 69 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 70 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 71 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 72 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 73 * Interrupt enable bits defined below. 74 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 75 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 76 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 77 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 78 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 79 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 80 */ 81 #define MACH_SR_COP_USABILITY 0xf0000000 82 #define MACH_SR_COP_0_BIT 0x10000000 83 #define MACH_SR_COP_1_BIT 0x20000000 84 #define MACH_SR_BOOT_EXC_VEC 0x00400000 85 #define MACH_SR_TLB_SHUTDOWN 0x00200000 86 #define MACH_SR_PARITY_ERR 0x00100000 87 #define MACH_SR_CACHE_MISS 0x00080000 88 #define MACH_SR_PARITY_ZERO 0x00040000 89 #define MACH_SR_SWAP_CACHES 0x00020000 90 #define MACH_SR_ISOL_CACHES 0x00010000 91 #define MACH_SR_KU_OLD 0x00000020 92 #define MACH_SR_INT_ENA_OLD 0x00000010 93 #define MACH_SR_KU_PREV 0x00000008 94 #define MACH_SR_INT_ENA_PREV 0x00000004 95 #define MACH_SR_KU_CUR 0x00000002 96 #define MACH_SR_INT_ENA_CUR 0x00000001 97 #define MACH_SR_MBZ 0x0f8000c0 98 99 /* 100 * The interrupt masks. 101 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 102 */ 103 #define MACH_INT_MASK 0xff00 104 #define MACH_INT_MASK_5 0x8000 105 #define MACH_INT_MASK_4 0x4000 106 #define MACH_INT_MASK_3 0x2000 107 #define MACH_INT_MASK_2 0x1000 108 #define MACH_INT_MASK_1 0x0800 109 #define MACH_INT_MASK_0 0x0400 110 #define MACH_HARD_INT_MASK 0xfc00 111 #define MACH_SOFT_INT_MASK_1 0x0200 112 #define MACH_SOFT_INT_MASK_0 0x0100 113 114 /* 115 * The bits in the context register. 116 */ 117 #define MACH_CNTXT_PTE_BASE 0xFFE00000 118 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 119 120 /* 121 * Location of exception vectors. 122 */ 123 #define MACH_RESET_EXC_VEC 0xBFC00000 124 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 125 #define MACH_GEN_EXC_VEC 0x80000080 126 127 /* 128 * Coprocessor 0 registers: 129 * 130 * MACH_COP_0_TLB_INDEX TLB index. 131 * MACH_COP_0_TLB_RANDOM TLB random. 132 * MACH_COP_0_TLB_LOW TLB entry low. 133 * MACH_COP_0_TLB_CONTEXT TLB context. 134 * MACH_COP_0_BAD_VADDR Bad virtual address. 135 * MACH_COP_0_TLB_HI TLB entry high. 136 * MACH_COP_0_STATUS_REG Status register. 137 * MACH_COP_0_CAUSE_REG Exception cause register. 138 * MACH_COP_0_EXC_PC Exception PC. 139 * MACH_COP_0_PRID Processor revision identifier. 140 */ 141 #define MACH_COP_0_TLB_INDEX $0 142 #define MACH_COP_0_TLB_RANDOM $1 143 #define MACH_COP_0_TLB_LOW $2 144 #define MACH_COP_0_TLB_CONTEXT $4 145 #define MACH_COP_0_BAD_VADDR $8 146 #define MACH_COP_0_TLB_HI $10 147 #define MACH_COP_0_STATUS_REG $12 148 #define MACH_COP_0_CAUSE_REG $13 149 #define MACH_COP_0_EXC_PC $14 150 #define MACH_COP_0_PRID $15 151 152 /* 153 * Values for the code field in a break instruction. 154 */ 155 #define MACH_BREAK_INSTR 0x0000000d 156 #define MACH_BREAK_VAL_MASK 0x03ff0000 157 #define MACH_BREAK_VAL_SHIFT 16 158 #define MACH_BREAK_KDB_VAL 512 159 #define MACH_BREAK_SSTEP_VAL 513 160 #define MACH_BREAK_BRKPT_VAL 514 161 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 162 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 163 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 164 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 165 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 166 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 167 168 /* 169 * Mininum and maximum cache sizes. 170 */ 171 #define MACH_MIN_CACHE_SIZE (16 * 1024) 172 #define MACH_MAX_CACHE_SIZE (256 * 1024) 173 174 /* 175 * The floating point version and status registers. 176 */ 177 #define MACH_FPC_ID $0 178 #define MACH_FPC_CSR $31 179 180 /* 181 * The floating point coprocessor status register bits. 182 */ 183 #define MACH_FPC_ROUNDING_BITS 0x00000003 184 #define MACH_FPC_ROUND_RN 0x00000000 185 #define MACH_FPC_ROUND_RZ 0x00000001 186 #define MACH_FPC_ROUND_RP 0x00000002 187 #define MACH_FPC_ROUND_RM 0x00000003 188 #define MACH_FPC_STICKY_BITS 0x0000007c 189 #define MACH_FPC_STICKY_INEXACT 0x00000004 190 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 191 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 192 #define MACH_FPC_STICKY_DIV0 0x00000020 193 #define MACH_FPC_STICKY_INVALID 0x00000040 194 #define MACH_FPC_ENABLE_BITS 0x00000f80 195 #define MACH_FPC_ENABLE_INEXACT 0x00000080 196 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 197 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 198 #define MACH_FPC_ENABLE_DIV0 0x00000400 199 #define MACH_FPC_ENABLE_INVALID 0x00000800 200 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 201 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 202 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 203 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 204 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 205 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 206 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 207 #define MACH_FPC_COND_BIT 0x00800000 208 #define MACH_FPC_MBZ_BITS 0xff7c0000 209 210 /* 211 * Constants to determine if have a floating point instruction. 212 */ 213 #define MACH_OPCODE_SHIFT 26 214 #define MACH_OPCODE_C1 0x11 215 216 /* 217 * The low part of the TLB entry. 218 */ 219 #define VMMACH_TLB_PF_NUM 0xfffff000 220 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 221 #define VMMACH_TLB_MOD_BIT 0x00000400 222 #define VMMACH_TLB_VALID_BIT 0x00000200 223 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 224 225 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 226 227 /* 228 * The high part of the TLB entry. 229 */ 230 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 231 #define VMMACH_TLB_PID 0x00000fc0 232 #define VMMACH_TLB_PID_SHIFT 6 233 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 234 235 /* 236 * The shift to put the index in the right spot. 237 */ 238 #define VMMACH_TLB_INDEX_SHIFT 8 239 240 /* 241 * The number of TLB entries and the first one that write random hits. 242 */ 243 #define VMMACH_NUM_TLB_ENTRIES 64 244 #define VMMACH_FIRST_RAND_ENTRY 8 245 246 /* 247 * The number of process id entries. 248 */ 249 #define VMMACH_NUM_PIDS 64 250 251 /* 252 * TLB probe return codes. 253 */ 254 #define VMMACH_TLB_NOT_FOUND 0 255 #define VMMACH_TLB_FOUND 1 256 #define VMMACH_TLB_FOUND_WITH_PATCH 2 257 #define VMMACH_TLB_PROBE_ERROR 3 258 259 /* 260 * Kernel virtual address for user page table entries 261 * (i.e., the address for the context register). 262 */ 263 #define VMMACH_PTE_BASE 0xFFC00000 264 265 #endif /* _MACHCONST */ 266