1 /* 2 * Copyright (c) 1992 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Ralph Campbell. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)machConst.h 7.1 (Berkeley) 01/07/92 11 * 12 * machConst.h -- 13 * 14 * Machine dependent constants. 15 * 16 * Copyright (C) 1989 Digital Equipment Corporation. 17 * Permission to use, copy, modify, and distribute this software and 18 * its documentation for any purpose and without fee is hereby granted, 19 * provided that the above copyright notice appears in all copies. 20 * Digital Equipment Corporation makes no representations about the 21 * suitability of this software for any purpose. It is provided "as is" 22 * without express or implied warranty. 23 * 24 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 25 * v 9.2 89/10/21 15:55:22 jhh Exp $ SPRITE (DECWRL) 26 * from: $Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 27 * v 1.2 89/08/15 18:28:21 rab Exp $ SPRITE (DECWRL) 28 * from: $Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 29 * v 9.1 89/09/18 17:33:00 shirriff Exp $ SPRITE (DECWRL) 30 */ 31 32 #ifndef _MACHCONST 33 #define _MACHCONST 34 35 #define MACH_KUSEG_ADDR 0x0 36 #define MACH_CACHED_MEMORY_ADDR 0x80000000 37 #define MACH_CACHED_FRAME_BUFFER_ADDR 0x8fc00000 38 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 39 #define MACH_UNCACHED_FRAME_BUFFER_ADDR 0xafc00000 40 #define MACH_PLANE_MASK_ADDR 0xb0000000 41 #define MACH_CURSOR_REG_ADDR 0xb1000000 42 #define MACH_COLOR_MAP_ADDR 0xb2000000 43 #define MACH_RESERVED_ADDR 0xb3000000 44 #define MACH_WRITE_ERROR_ADDR 0xb7000000 45 #define MACH_NETWORK_INTERFACE_ADDR 0xb8000000 46 #define MACH_NETWORK_BUFFER_ADDR 0xb9000000 47 #define MACH_SCSI_INTERFACE_ADDR 0xba000000 48 #define MACH_SCSI_BUFFER_ADDR 0xbb000000 49 #define MACH_SERIAL_INTERFACE_ADDR 0xbc000000 50 #define MACH_CLOCK_ADDR 0xbd000000 51 #define MACH_SYS_CSR_ADDR 0xbe000000 52 #define MACH_ROM_ADDR 0xbf000000 53 #define MACH_KSEG2_ADDR 0xc0000000 54 55 #define MACH_CODE_START 0x80030000 56 57 /* 58 * The bits in the cause register. 59 * 60 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 61 * MACH_CR_COP_ERR Coprocessor error. 62 * Interrupt pending bits defined below. 63 * MACH_CR_EXC_CODE The exception type (see exception codes below). 64 */ 65 #define MACH_CR_BR_DELAY 0x80000000 66 #define MACH_CR_COP_ERR 0x30000000 67 #define MACH_CR_EXC_CODE 0x0000003C 68 #define MACH_CR_EXC_CODE_SHIFT 2 69 70 /* 71 * The bits in the status register. All bits are active when set to 1. 72 * 73 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 74 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 75 * MACH_SR_TLB_SHUTDOWN TLB disabled. 76 * MACH_SR_PARITY_ERR Parity error. 77 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 78 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 79 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 80 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 81 * Interrupt enable bits defined below. 82 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 83 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 84 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 85 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 86 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 87 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 88 */ 89 #define MACH_SR_COP_USABILITY 0xf0000000 90 #define MACH_SR_COP_0_BIT 0x10000000 91 #define MACH_SR_COP_1_BIT 0x20000000 92 #define MACH_SR_BOOT_EXC_VEC 0x00400000 93 #define MACH_SR_TLB_SHUTDOWN 0x00200000 94 #define MACH_SR_PARITY_ERR 0x00100000 95 #define MACH_SR_CACHE_MISS 0x00080000 96 #define MACH_SR_PARITY_ZERO 0x00040000 97 #define MACH_SR_SWAP_CACHES 0x00020000 98 #define MACH_SR_ISOL_CACHES 0x00010000 99 #define MACH_SR_KU_OLD 0x00000020 100 #define MACH_SR_INT_ENA_OLD 0x00000010 101 #define MACH_SR_KU_PREV 0x00000008 102 #define MACH_SR_INT_ENA_PREV 0x00000004 103 #define MACH_SR_KU_CUR 0x00000002 104 #define MACH_SR_INT_ENA_CUR 0x00000001 105 #define MACH_SR_MBZ 0x0f8000c0 106 107 /* 108 * The interrupt masks. 109 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 110 */ 111 #define MACH_INT_MASK 0xff00 112 #define MACH_INT_MASK_5 0x8000 113 #define MACH_INT_MASK_4 0x4000 114 #define MACH_INT_MASK_3 0x2000 115 #define MACH_INT_MASK_2 0x1000 116 #define MACH_INT_MASK_1 0x0800 117 #define MACH_INT_MASK_0 0x0400 118 #define MACH_HARD_INT_MASK 0xfc00 119 #define MACH_SOFT_INT_MASK_1 0x0200 120 #define MACH_SOFT_INT_MASK_0 0x0100 121 122 /* 123 * The system control status register. 124 */ 125 #define MACH_CSR_MONO 0x0800 126 #define MACH_CSR_MEM_ERR 0x0400 127 #define MACH_CSR_VINT 0x0200 128 #define MACH_CSR_MBZ 0x9800 129 130 /* 131 * The bits in the context register. 132 */ 133 #define MACH_CNTXT_PTE_BASE 0xFFE00000 134 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 135 136 /* 137 * Location of exception vectors. 138 */ 139 #define MACH_RESET_EXC_VEC 0xBFC00000 140 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 141 #define MACH_GEN_EXC_VEC 0x80000080 142 143 /* 144 * Coprocessor 0 registers: 145 * 146 * MACH_COP_0_TLB_INDEX TLB index. 147 * MACH_COP_0_TLB_RANDOM TLB random. 148 * MACH_COP_0_TLB_LOW TLB entry low. 149 * MACH_COP_0_TLB_CONTEXT TLB context. 150 * MACH_COP_0_BAD_VADDR Bad virtual address. 151 * MACH_COP_0_TLB_HI TLB entry high. 152 * MACH_COP_0_STATUS_REG Status register. 153 * MACH_COP_0_CAUSE_REG Exception cause register. 154 * MACH_COP_0_EXC_PC Exception PC. 155 * MACH_COP_0_PRID Processor revision identifier. 156 */ 157 #define MACH_COP_0_TLB_INDEX $0 158 #define MACH_COP_0_TLB_RANDOM $1 159 #define MACH_COP_0_TLB_LOW $2 160 #define MACH_COP_0_TLB_CONTEXT $4 161 #define MACH_COP_0_BAD_VADDR $8 162 #define MACH_COP_0_TLB_HI $10 163 #define MACH_COP_0_STATUS_REG $12 164 #define MACH_COP_0_CAUSE_REG $13 165 #define MACH_COP_0_EXC_PC $14 166 #define MACH_COP_0_PRID $15 167 168 /* 169 * Values for the code field in a break instruction. 170 */ 171 #define MACH_BREAK_CODE_FIELD 0x03ffffc0 172 #define MACH_BREAKPOINT_VAL 0 173 #define MACH_SIG_RET_VAL 0x00010000 174 #define MACH_SSTEP_VAL 0x00020000 175 176 /* 177 * Constants to differentiate between a breakpoint trap and all others. 178 */ 179 #define MACH_OTHER_TRAP_TYPE 0 180 #define MACH_BRKPT_TRAP 1 181 182 /* 183 * Mininum and maximum cache sizes. 184 */ 185 #define MACH_MIN_CACHE_SIZE (16 * 1024) 186 #define MACH_MAX_CACHE_SIZE (64 * 1024) 187 188 /* 189 * The floating point version and status registers. 190 */ 191 #define MACH_FPC_ID $0 192 #define MACH_FPC_CSR $31 193 194 /* 195 * The floating point coprocessor status register bits. 196 */ 197 #define MACH_FPC_ROUNDING_BITS 0x00000003 198 #define MACH_FPC_ROUND_RN 0x00000000 199 #define MACH_FPC_ROUND_RZ 0x00000001 200 #define MACH_FPC_ROUND_RP 0x00000002 201 #define MACH_FPC_ROUND_RM 0x00000003 202 #define MACH_FPC_STICKY_BITS 0x0000007c 203 #define MACH_FPC_STICKY_INEXACT 0x00000004 204 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 205 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 206 #define MACH_FPC_STICKY_DIV0 0x00000020 207 #define MACH_FPC_STICKY_INVALID 0x00000040 208 #define MACH_FPC_ENABLE_BITS 0x00000f80 209 #define MACH_FPC_ENABLE_INEXACT 0x00000080 210 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 211 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 212 #define MACH_FPC_ENABLE_DIV0 0x00000400 213 #define MACH_FPC_ENABLE_INVALID 0x00000800 214 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 215 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 216 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 217 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 218 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 219 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 220 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 221 #define MACH_FPC_COND_BIT 0x00800000 222 #define MACH_FPC_MBZ_BITS 0xff7c0000 223 224 /* 225 * Constants to determine if have a floating point instruction. 226 */ 227 #define MACH_OPCODE_SHIFT 26 228 #define MACH_OPCODE_C1 0x11 229 230 /* 231 * The low part of the TLB entry. 232 */ 233 #define VMMACH_TLB_PF_NUM 0xfffff000 234 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 235 #define VMMACH_TLB_MOD_BIT 0x00000400 236 #define VMMACH_TLB_VALID_BIT 0x00000200 237 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 238 239 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 240 241 /* 242 * The high part of the TLB entry. 243 */ 244 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 245 #define VMMACH_TLB_PID 0x00000fc0 246 #define VMMACH_TLB_PID_SHIFT 6 247 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 248 249 /* 250 * The shift to put the index in the right spot. 251 */ 252 #define VMMACH_TLB_INDEX_SHIFT 8 253 254 /* 255 * The number of TLB entries and the first one that write random hits. 256 */ 257 #define VMMACH_NUM_TLB_ENTRIES 64 258 #define VMMACH_FIRST_RAND_ENTRY 8 259 260 /* 261 * The number of process id entries. 262 */ 263 #define VMMACH_NUM_PIDS 64 264 265 /* 266 * TLB probe return codes. 267 */ 268 #define VMMACH_TLB_NOT_FOUND 0 269 #define VMMACH_TLB_FOUND 1 270 #define VMMACH_TLB_FOUND_WITH_PATCH 2 271 #define VMMACH_TLB_PROBE_ERROR 3 272 273 /* 274 * Kernel virtual address for user page table entries 275 * (i.e., the address for the context register). 276 */ 277 #define VMMACH_PTE_BASE 0xFFC00000 278 279 #endif /* _MACHCONST */ 280