1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * The Mach Operating System project at Carnegie-Mellon University, 7 * Ralph Campbell and Rick Macklem. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)asic.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* 15 * Mach Operating System 16 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 17 * All Rights Reserved. 18 * 19 * Permission to use, copy, modify and distribute this software and 20 * its documentation is hereby granted, provided that both the copyright 21 * notice and this permission notice appear in all copies of the 22 * software, derivative works or modified versions, and any portions 23 * thereof, and that both notices appear in supporting documentation. 24 * 25 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 26 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 27 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 28 * 29 * Carnegie Mellon requests users of this software to return to 30 * 31 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 32 * School of Computer Science 33 * Carnegie Mellon University 34 * Pittsburgh PA 15213-3890 35 * 36 * any improvements or extensions that they make and grant Carnegie the 37 * rights to redistribute these changes. 38 */ 39 /* 40 * HISTORY 41 * $Log: asic.h,v $ 42 * Revision 2.2 92/03/02 18:33:32 rpd 43 * Created, from the DEC specs: 44 * "IO Controller ASIC Functional Specifications" 45 * Workstation Systems Engineering, Palo Alto, CA. Feb 1, 1991. 46 * [92/01/17 af] 47 * 48 */ 49 /* 50 * File: asic.h 51 * Author: Alessandro Forin, Carnegie Mellon University 52 * Date: 1/92 53 * 54 * Definitions specific to the IO Controller ASIC, used 55 * on 3min and MAXine motherboards. 56 */ 57 58 #ifndef MIPS_ASIC_H 59 #define MIPS_ASIC_H 1 60 61 /* 62 * Slot definitions 63 */ 64 65 #define ASIC_SLOT_0_START 0x000000 66 #define ASIC_SLOT_1_START 0x040000 67 #define ASIC_SLOT_2_START 0x080000 68 #define ASIC_SLOT_3_START 0x0c0000 69 #define ASIC_SLOT_4_START 0x100000 70 #define ASIC_SLOT_5_START 0x140000 71 #define ASIC_SLOT_6_START 0x180000 72 #define ASIC_SLOT_7_START 0x1c0000 73 #define ASIC_SLOT_8_START 0x200000 74 #define ASIC_SLOT_9_START 0x240000 75 #define ASIC_SLOT_10_START 0x280000 76 #define ASIC_SLOT_11_START 0x2c0000 77 #define ASIC_SLOT_12_START 0x300000 78 #define ASIC_SLOT_13_START 0x340000 79 #define ASIC_SLOT_14_START 0x380000 80 #define ASIC_SLOT_15_START 0x3c0000 81 #define ASIC_SLOTS_END 0x3fffff 82 83 /* 84 * Register offsets (slot 1) 85 */ 86 87 #define ASIC_SCSI_DMAPTR ASIC_SLOT_1_START+0x000 88 #define ASIC_SCSI_NEXTPTR ASIC_SLOT_1_START+0x010 89 #define ASIC_LANCE_DMAPTR ASIC_SLOT_1_START+0x020 90 #define ASIC_SCC_T1_DMAPTR ASIC_SLOT_1_START+0x030 91 #define ASIC_SCC_R1_DMAPTR ASIC_SLOT_1_START+0x040 92 #define ASIC_SCC_T2_DMAPTR ASIC_SLOT_1_START+0x050 93 #define ASIC_SCC_R2_DMAPTR ASIC_SLOT_1_START+0x060 94 #define ASIC_FLOPPY_DMAPTR ASIC_SLOT_1_START+0x070 95 #define ASIC_ISDN_X_DMAPTR ASIC_SLOT_1_START+0x080 96 #define ASIC_ISDN_X_NEXTPTR ASIC_SLOT_1_START+0x090 97 #define ASIC_ISDN_R_DMAPTR ASIC_SLOT_1_START+0x0a0 98 #define ASIC_ISDN_R_NEXTPTR ASIC_SLOT_1_START+0x0b0 99 #define ASIC_BUFF0 ASIC_SLOT_1_START+0x0c0 100 #define ASIC_BUFF1 ASIC_SLOT_1_START+0x0d0 101 #define ASIC_BUFF2 ASIC_SLOT_1_START+0x0e0 102 #define ASIC_BUFF3 ASIC_SLOT_1_START+0x0f0 103 #define ASIC_CSR ASIC_SLOT_1_START+0x100 104 #define ASIC_INTR ASIC_SLOT_1_START+0x110 105 #define ASIC_IMSK ASIC_SLOT_1_START+0x120 106 #define ASIC_CURADDR ASIC_SLOT_1_START+0x130 107 #define ASIC_ISDN_X_DATA ASIC_SLOT_1_START+0x140 108 #define ASIC_ISDN_R_DATA ASIC_SLOT_1_START+0x150 109 #define ASIC_LANCE_DECODE ASIC_SLOT_1_START+0x160 110 #define ASIC_SCSI_DECODE ASIC_SLOT_1_START+0x170 111 #define ASIC_SCC0_DECODE ASIC_SLOT_1_START+0x180 112 #define ASIC_SCC1_DECODE ASIC_SLOT_1_START+0x190 113 #define ASIC_FLOPPY_DECODE ASIC_SLOT_1_START+0x1a0 114 #define ASIC_SCSI_SCR ASIC_SLOT_1_START+0x1b0 115 #define ASIC_SCSI_SDR0 ASIC_SLOT_1_START+0x1c0 116 #define ASIC_SCSI_SDR1 ASIC_SLOT_1_START+0x1d0 117 118 /* system Status and Control register (SSR) */ 119 120 #define ASIC_CSR_DMAEN_T1 0x80000000 /* rw */ 121 #define ASIC_CSR_DMAEN_R1 0x40000000 /* rw */ 122 #define ASIC_CSR_DMAEN_T2 0x20000000 /* rw */ 123 #define ASIC_CSR_DMAEN_R2 0x10000000 /* rw */ 124 #define ASIC_CSR_xxx 0x0f800000 /* reserved */ 125 #define ASIC_CSR_FLOPPY_DIR 0x00400000 /* rw */ 126 #define ASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw */ 127 #define ASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */ 128 #define ASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */ 129 #define ASIC_CSR_SCSI_DIR 0x00040000 /* rw */ 130 #define ASIC_CSR_DMAEN_SCSI 0x00020000 /* rw */ 131 #define ASIC_CSR_DMAEN_LANCE 0x00010000 /* rw */ 132 /* low 16 bits are rw gp outputs */ 133 134 /* system Interrupt register (and interrupt mask register) */ 135 136 #define ASIC_INTR_T1_PAGE_END 0x80000000 /* rz */ 137 #define ASIC_INTR_T1_READ_E 0x40000000 /* rz */ 138 #define ASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */ 139 #define ASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */ 140 #define ASIC_INTR_T2_PAGE_END 0x08000000 /* rz */ 141 #define ASIC_INTR_T2_READ_E 0x04000000 /* rz */ 142 #define ASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */ 143 #define ASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */ 144 #define ASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz */ 145 #define ASIC_INTR_ISDN_PTR_LOAD 0x00400000 /* rz */ 146 #define ASIC_INTR_ISDN_OVRUN 0x00200000 /* rz */ 147 #define ASIC_INTR_ISDN_READ_E 0x00100000 /* rz */ 148 #define ASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz */ 149 #define ASIC_INTR_SCSI_OVRUN 0x00040000 /* rz */ 150 #define ASIC_INTR_SCSI_READ_E 0x00020000 /* rz */ 151 #define ASIC_INTR_LANCE_READ_E 0x00010000 /* rz */ 152 /* low 16 are gp interrupts */ 153 154 /* DMA pointer registers (SCSI, Comm, ...) */ 155 156 #define ASIC_DMAPTR_MASK 0xffffffe0 157 #define ASIC_DMAPTR_SHIFT 5 158 # define ASIC_DMAPTR_SET(reg,val) \ 159 (reg) = (((val)<<ASIC_DMAPTR_SHIFT)&ASIC_DMAPTR_MASK) 160 # define ASIC_DMAPTR_GET(reg,val) \ 161 (val) = (((reg)&ASIC_DMAPTR_MASK)>>ASIC_DMAPTR_SHIFT) 162 #define ASIC_DMA_ADDR(p) (((unsigned)p) << (5-2)) 163 164 /* For the LANCE DMA pointer register initialization the above suffices */ 165 166 /* More SCSI DMA registers */ 167 168 #define ASIC_SCR_STATUS 0x00000004 169 #define ASIC_SCR_WORD 0x00000003 170 171 /* Various Decode registers */ 172 173 #define ASIC_DECODE_HW_ADDRESS 0x000003f0 174 #define ASIC_DECODE_CHIP_SELECT 0x0000000f 175 176 /* 177 * Asic register addresses at offset from base. 178 */ 179 #define ASIC_REG_SCSI_DMAPTR(base) ((base) + ASIC_SCSI_DMAPTR) 180 #define ASIC_REG_SCSI_DMANPTR(base) ((base) + ASIC_SCSI_NEXTPTR) 181 #define ASIC_REG_LANCE_DMAPTR(base) ((base) + ASIC_LANCE_DMAPTR) 182 #define ASIC_REG_SCC_T1_DMAPTR(base) ((base) + ASIC_SCC_T1_DMAPTR) 183 #define ASIC_REG_SCC_R1_DMAPTR(base) ((base) + ASIC_SCC_R1_DMAPTR) 184 #define ASIC_REG_SCC_T2_DMAPTR(base) ((base) + ASIC_SCC_T2_DMAPTR) 185 #define ASIC_REG_SCC_R2_DMAPTR(base) ((base) + ASIC_SCC_R2_DMAPTR) 186 #define ASIC_REG_FLOPPY_DMAPTR(base) ((base) + ASIC_FLOPPY_DMAPTR) 187 #define ASIC_REG_ISDN_X_DMAPTR(base) ((base) + ASIC_ISDN_X_DMAPTR) 188 #define ASIC_REG_ISDN_X_NEXTPTR(base) ((base) + ASIC_ISDN_X_NEXTPTR) 189 #define ASIC_REG_ISDN_R_DMAPTR(base) ((base) + ASIC_ISDN_R_DMAPTR) 190 #define ASIC_REG_ISDN_R_NEXTPTR(base) ((base) + ASIC_ISDN_R_NEXTPTR) 191 #define ASIC_REG_BUFF0(base) ((base) + ASIC_BUFF0) 192 #define ASIC_REG_BUFF1(base) ((base) + ASIC_BUFF1) 193 #define ASIC_REG_BUFF2(base) ((base) + ASIC_BUFF2) 194 #define ASIC_REG_BUFF3(base) ((base) + ASIC_BUFF3) 195 #define ASIC_REG_CSR(base) ((base) + ASIC_CSR) 196 #define ASIC_REG_INTR(base) ((base) + ASIC_INTR) 197 #define ASIC_REG_IMSK(base) ((base) + ASIC_IMSK) 198 #define ASIC_REG_CURADDR(base) ((base) + ASIC_CURADDR) 199 #define ASIC_REG_ISDN_X_DATA(base) ((base) + ASIC_ISDN_X_DATA) 200 #define ASIC_REG_ISDN_R_DATA(base) ((base) + ASIC_ISDN_R_DATA) 201 #define ASIC_REG_LANCE_DECODE(base) ((base) + ASIC_LANCE_DECODE) 202 #define ASIC_REG_SCSI_DECODE(base) ((base) + ASIC_SCSI_DECODE) 203 #define ASIC_REG_SCC0_DECODE(base) ((base) + ASIC_SCC0_DECODE) 204 #define ASIC_REG_SCC1_DECODE(base) ((base) + ASIC_SCC1_DECODE) 205 #define ASIC_REG_FLOPPY_DECODE(base) ((base) + ASIC_FLOPPY_DECODE) 206 #define ASIC_REG_SCSI_SCR(base) ((base) + ASIC_SCSI_SCR) 207 #define ASIC_REG_SCSI_SDR0(base) ((base) + ASIC_SCSI_SDR0) 208 #define ASIC_REG_SCSI_SDR1(base) ((base) + ASIC_SCSI_SDR1) 209 210 /* 211 * And slot assignments. 212 */ 213 #define ASIC_SYS_ETHER_ADDRESS(base) ((base) + ASIC_SLOT_2_START) 214 #define ASIC_SYS_LANCE(base) ((base) + ASIC_SLOT_3_START) 215 #endif /* MIPS_ASIC_H */ 216