1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * The Mach Operating System project at Carnegie-Mellon University, 7 * Ralph Campbell and Rick Macklem. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)kmin.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* 15 * Mach Operating System 16 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 17 * All Rights Reserved. 18 * 19 * Permission to use, copy, modify and distribute this software and 20 * its documentation is hereby granted, provided that both the copyright 21 * notice and this permission notice appear in all copies of the 22 * software, derivative works or modified versions, and any portions 23 * thereof, and that both notices appear in supporting documentation. 24 * 25 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 26 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 27 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 28 * 29 * Carnegie Mellon requests users of this software to return to 30 * 31 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 32 * School of Computer Science 33 * Carnegie Mellon University 34 * Pittsburgh PA 15213-3890 35 * 36 * any improvements or extensions that they make and grant Carnegie the 37 * rights to redistribute these changes. 38 */ 39 /* 40 * HISTORY 41 * $Log: kmin.h,v $ 42 * Revision 2.3 92/03/02 18:33:43 rpd 43 * Split out the ASIC defns into separate file, which is 44 * in common with MAXine. Added some nitwits defines. 45 * [92/03/02 02:28:27 af] 46 * 47 * Revision 2.2 91/08/24 12:21:08 af 48 * Documented new SCSI registers, which were missing in the 3min prototype. 49 * [91/08/22 11:14:57 af] 50 * 51 * Created, from the DEC specs: 52 * "3MIN System Module Functional Specification" Revision 1.7 53 * Workstation Systems Engineering, Palo Alto, CA. Sept 14, 1990. 54 * "KN02BA Daughter Card Functional Specification" Revision 1.0 55 * Workstation Systems Engineering, Palo Alto, CA. Aug 14, 1990. 56 * [91/06/21 af] 57 * 58 */ 59 /* 60 * File: kmin.h 61 * Author: Alessandro Forin, Carnegie Mellon University 62 * Date: 6/91 63 * 64 * Definitions specific to the KN02BA/KN02DA processors and 3MIN 65 * system module (54-20604-01) 66 */ 67 68 #ifndef MIPS_KMIN_H 69 #define MIPS_KMIN_H 1 70 71 /* 72 * 3MIN's Physical address space 73 */ 74 75 #define KMIN_PHYS_MIN 0x00000000 /* 512 Meg */ 76 #define KMIN_PHYS_MAX 0x1fffffff 77 78 /* 79 * Memory map 80 */ 81 82 #define KMIN_PHYS_MEMORY_START 0x00000000 83 #define KMIN_PHYS_MEMORY_END 0x07ffffff /* 128 Meg in 8 slots */ 84 85 /* 86 * I/O map 87 */ 88 89 #define KMIN_PHYS_RESERVED 0x08000000 /* Reserved */ 90 /* 64 Meg */ 91 92 #define KMIN_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ 93 #define KMIN_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ 94 #define KMIN_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ 95 #define KMIN_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ 96 97 #define KMIN_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ 98 #define KMIN_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ 99 100 #define KMIN_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ 101 #define KMIN_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ 102 103 #define KMIN_PHYS_TC_2_START 0x18000000 /* TURBOchannel, slot 2 */ 104 #define KMIN_PHYS_TC_2_END 0x1bffffff /* 64 Meg, option2 */ 105 106 #define KMIN_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ 107 #define KMIN_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ 108 109 #define KMIN_PHYS_TC_START KMIN_PHYS_TC_0_START 110 #define KMIN_PHYS_TC_END KMIN_PHYS_TC_3_END /* 256 Meg */ 111 112 #define KMIN_TC_NSLOTS 4 113 #define KMIN_TC_MIN 0 114 #define KMIN_TC_MAX 2 /* don't look at system slot */ 115 116 /* Pseudo-TCslots */ 117 #define KMIN_SCSI_SLOT 3 118 #define KMIN_LANCE_SLOT 4 119 #define KMIN_SCC1_SLOT 5 120 #define KMIN_SCC0_SLOT 6 121 #define KMIN_ASIC_SLOT 7 122 123 /* 124 * System module space (IO ASIC) 125 */ 126 127 #define KMIN_SYS_ASIC ( KMIN_PHYS_TC_3_START + 0x0000000 ) 128 129 #define KMIN_SYS_ROM_START ( KMIN_SYS_ASIC + ASIC_SLOT_0_START ) 130 131 #define KMIN_SYS_ASIC_REGS ( KMIN_SYS_ASIC + ASIC_SLOT_1_START ) 132 133 #define KMIN_SYS_ETHER_ADDRESS ( KMIN_SYS_ASIC + ASIC_SLOT_2_START ) 134 135 #define KMIN_SYS_LANCE ( KMIN_SYS_ASIC + ASIC_SLOT_3_START ) 136 137 #define KMIN_SYS_SCC_0 ( KMIN_SYS_ASIC + ASIC_SLOT_4_START ) 138 139 #define KMIN_SYS_SCC_1 ( KMIN_SYS_ASIC + ASIC_SLOT_6_START ) 140 141 #define KMIN_SYS_CLOCK ( KMIN_SYS_ASIC + ASIC_SLOT_8_START ) 142 143 #define KMIN_SYS_SCSI ( KMIN_SYS_ASIC + ASIC_SLOT_12_START ) 144 145 #define KMIN_SYS_SCSI_DMA ( KMIN_SYS_ASIC + ASIC_SLOT_14_START ) 146 147 #define KMIN_SYS_BOOT_ROM_START ( KMIN_PHYS_TC_3_START + 0x3c00000 ) 148 #define KMIN_SYS_BOOT_ROM_END ( KMIN_PHYS_TC_3_START + 0x3c40000 ) 149 150 /* 151 * Interrupts 152 */ 153 154 #define KMIN_INT_FPA IP_LEV7 /* Floating Point coproc */ 155 #define KMIN_INT_HALTB IP_LEV6 /* Halt button */ 156 #define KMIN_INT_TC3 IP_LEV5 /* TC slot 3, system */ 157 #define KMIN_INT_TC2 IP_LEV4 /* TC option slot 2 */ 158 #define KMIN_INT_TC1 IP_LEV3 /* TC option slot 1 */ 159 #define KMIN_INT_TC0 IP_LEV2 /* TC option slot 0 */ 160 161 /* 162 * System registers addresses (MREG and CREG space, and IO Control ASIC) 163 */ 164 165 #define KMIN_REG_MER 0x0c400000 /* Memory error register */ 166 #define KMIN_REG_MSR 0x0c800000 /* Memory size register */ 167 168 #define KMIN_REG_CNFG 0x0e000000 /* Config mem timeouts */ 169 #define KMIN_REG_AER 0x0e000004 /* Address error register */ 170 #define KMIN_REG_BOOT 0x0e000008 /* Boot 0 register */ 171 #define KMIN_REG_TIMEOUT 0x0e00000c /* Mem access timeout reg */ 172 173 #define KMIN_REG_SCSI_DMAPTR ( KMIN_SYS_ASIC + ASIC_SCSI_DMAPTR ) 174 #define KMIN_REG_SCSI_DMANPTR ( KMIN_SYS_ASIC + ASIC_SCSI_NEXTPTR ) 175 #define KMIN_REG_LANCE_DMAPTR ( KMIN_SYS_ASIC + ASIC_LANCE_DMAPTR ) 176 #define KMIN_REG_SCC_T1_DMAPTR ( KMIN_SYS_ASIC + ASIC_SCC_T1_DMAPTR ) 177 #define KMIN_REG_SCC_R1_DMAPTR ( KMIN_SYS_ASIC + ASIC_SCC_R1_DMAPTR ) 178 #define KMIN_REG_SCC_T2_DMAPTR ( KMIN_SYS_ASIC + ASIC_SCC_T2_DMAPTR ) 179 #define KMIN_REG_SCC_R2_DMAPTR ( KMIN_SYS_ASIC + ASIC_SCC_R2_DMAPTR ) 180 #define KMIN_REG_CSR ( KMIN_SYS_ASIC + ASIC_CSR ) 181 #define KMIN_REG_INTR ( KMIN_SYS_ASIC + ASIC_INTR ) 182 #define KMIN_REG_IMSK ( KMIN_SYS_ASIC + ASIC_IMSK ) 183 #define KMIN_REG_CURADDR ( KMIN_SYS_ASIC + ASIC_CURADDR ) 184 185 #define KMIN_REG_LANCE_DECODE ( KMIN_SYS_ASIC + ASIC_LANCE_DECODE ) 186 #define KMIN_REG_SCSI_DECODE ( KMIN_SYS_ASIC + ASIC_SCSI_DECODE ) 187 #define KMIN_REG_SCC0_DECODE ( KMIN_SYS_ASIC + ASIC_SCC0_DECODE ) 188 #define KMIN_REG_SCC1_DECODE ( KMIN_SYS_ASIC + ASIC_SCC1_DECODE ) 189 # define KMIN_LANCE_CONFIG 3 190 # define KMIN_SCSI_CONFIG 14 191 # define KMIN_SCC0_CONFIG (0x10|4) 192 # define KMIN_SCC1_CONFIG (0x10|6) 193 194 #define KMIN_REG_SCSI_SCR ( KMIN_SYS_ASIC + ASIC_SCSI_SCR ) 195 #define KMIN_REG_SCSI_SDR0 ( KMIN_SYS_ASIC + ASIC_SCSI_SDR0 ) 196 #define KMIN_REG_SCSI_SDR1 ( KMIN_SYS_ASIC + ASIC_SCSI_SDR1 ) 197 198 199 /* 200 * System registers defines (MREG and CREG) 201 */ 202 203 /* Memory error register */ 204 205 #define KMIN_MER_xxx 0xfffe30ff /* undefined */ 206 #define KMIN_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ 207 #define KMIN_MER_TLEN 0x00008000 /* rw: Xfer length error */ 208 #define KMIN_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ 209 #define KMIN_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ 210 # define KMIN_LASTB31 0x00000800 /* upper byte of word */ 211 # define KMIN_LASTB23 0x00000400 /* .. through .. */ 212 # define KMIN_LASTB15 0x00000200 /* .. the .. */ 213 # define KMIN_LASTB07 0x00000100 /* .. lower byte */ 214 215 /* Memory size register */ 216 217 #define KMIN_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ 218 #define KMIN_MSR_xxx 0xffffdfff /* undefined */ 219 220 /* NOTES 221 222 Memory access priority is, from higher to lower: 223 - DRAM refresh 224 - IO DMA (IO Control ASIC) 225 - Processor 226 - Slot 2 DMA 227 - Slot 1 DMA 228 - Slot 0 DMA 229 230 Memory performance is (with 80ns mem cycles) 231 - single word read 5 cyc 10.0 Mb/s 232 - word write 3 cyc 16.7 Mb/s 233 - single byte write 3 cyc 4.2 Mb/s 234 - 64w DMA read 68 cyc 47.1 Mb/s 235 - 64w DMA write 66 cyc 48.5 Mb/s 236 - Refresh 5 cyc N/A 237 */ 238 239 /* Timeout config register */ 240 241 #define KMIN_CNFG_VALUE_12Mhz 127 242 #define KMIN_CNFG_VALUE_25Mhz 0 243 244 /* Address error register */ 245 246 #define KMIN_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ 247 248 /* Boot 0 register */ 249 250 #define KMIN_BOOT_FROM_SLOT0 0x00000001 /* rw: diag board boot */ 251 252 /* Memory access timeout interrupt register */ 253 254 #define KMIN_TIMEO_INTR 0x00000001 /* rc: intr pending */ 255 256 /* 257 * More system registers defines (IO Control ASIC) 258 */ 259 260 /* (re)defines for the system Status and Control register (SSR) */ 261 262 #define KMIN_CSR_DMAEN_T1 ASIC_CSR_DMAEN_T1 263 #define KMIN_CSR_DMAEN_R1 ASIC_CSR_DMAEN_R1 264 #define KMIN_CSR_DMAEN_T2 ASIC_CSR_DMAEN_T2 265 #define KMIN_CSR_DMAEN_R2 ASIC_CSR_DMAEN_R2 266 #define KMIN_CSR_SCSI_DIR ASIC_CSR_SCSI_DIR 267 #define KMIN_CSR_DMAEN_SCSI ASIC_CSR_DMAEN_SCSI 268 #define KMIN_CSR_DMAEN_LANCE ASIC_CSR_DMAEN_LANCE 269 #define KMIN_CSR_DIAGDN 0x00008000 /* rw */ 270 #define KMIN_CSR_TXDIS_2 0x00004000 /* rw */ 271 #define KMIN_CSR_TXDIS_1 0x00002000 /* rw */ 272 #define KMIN_CSR_SCC_ENABLE 0x00000800 /* rw */ 273 #define KMIN_CSR_RTC_ENABLE 0x00000400 /* rw */ 274 #define KMIN_CSR_SCSI_ENABLE 0x00000200 /* rw */ 275 #define KMIN_CSR_LANCE_ENABLE 0x00000100 /* rw */ 276 #define KMIN_CSR_LEDS 0x000000ff /* rw */ 277 278 /* (re)defines for the System Interrupt and Mask Registers */ 279 280 #define KMIN_INTR_T1_PAGE_END ASIC_INTR_T1_PAGE_END 281 #define KMIN_INTR_T1_READ_E ASIC_INTR_T1_READ_E 282 #define KMIN_INTR_R1_HALF_PAGE ASIC_INTR_R1_HALF_PAGE 283 #define KMIN_INTR_R1_DMA_OVRUN ASIC_INTR_R1_DMA_OVRUN 284 #define KMIN_INTR_T2_PAGE_END ASIC_INTR_T2_PAGE_END 285 #define KMIN_INTR_T2_READ_E ASIC_INTR_T2_READ_E 286 #define KMIN_INTR_R2_HALF_PAGE ASIC_INTR_R2_HALF_PAGE 287 #define KMIN_INTR_R2_DMA_OVRUN ASIC_INTR_R2_DMA_OVRUN 288 #define KMIN_INTR_SCSI_PTR_LOAD ASIC_INTR_SCSI_PTR_LOAD 289 #define KMIN_INTR_SCSI_OVRUN ASIC_INTR_SCSI_OVRUN 290 #define KMIN_INTR_SCSI_READ_E ASIC_INTR_SCSI_READ_E 291 #define KMIN_INTR_LANCE_READ_E ASIC_INTR_LANCE_READ_E 292 #define KMIN_INTR_NVR_JUMPER 0x00004000 /* ro */ 293 #define KMIN_INTR_TIMEOUT 0x00001000 /* ro */ 294 #define KMIN_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 295 #define KMIN_INTR_SCSI 0x00000200 /* ro */ 296 #define KMIN_INTR_LANCE 0x00000100 /* ro */ 297 #define KMIN_INTR_SCC_1 0x00000080 /* ro */ 298 #define KMIN_INTR_SCC_0 0x00000040 /* ro */ 299 #define KMIN_INTR_CLOCK 0x00000020 /* ro */ 300 #define KMIN_INTR_PSWARN 0x00000010 /* ro */ 301 #define KMIN_INTR_SCSI_FIFO 0x00000004 /* ro */ 302 #define KMIN_INTR_PBNC 0x00000002 /* ro */ 303 #define KMIN_INTR_PBNO 0x00000001 /* ro */ 304 #define KMIN_INTR_ASIC 0xff0f0004 305 #define KMIN_IM0 0xff0f13f0 /* all good ones enabled */ 306 307 #endif /* MIPS_KMIN_H */ 308