1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * The Mach Operating System project at Carnegie-Mellon University, 7 * Ralph Campbell and Rick Macklem. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)kn02.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* 15 * Mach Operating System 16 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 17 * All Rights Reserved. 18 * 19 * Permission to use, copy, modify and distribute this software and 20 * its documentation is hereby granted, provided that both the copyright 21 * notice and this permission notice appear in all copies of the 22 * software, derivative works or modified versions, and any portions 23 * thereof, and that both notices appear in supporting documentation. 24 * 25 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 26 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 27 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 28 * 29 * Carnegie Mellon requests users of this software to return to 30 * 31 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 32 * School of Computer Science 33 * Carnegie Mellon University 34 * Pittsburgh PA 15213-3890 35 * 36 * any improvements or extensions that they make and grant Carnegie the 37 * rights to redistribute these changes. 38 */ 39 /* 40 * HISTORY 41 * $Log: kn02.h,v $ 42 * Revision 2.5 91/05/14 17:23:30 mrt 43 * Correcting copyright 44 * 45 * Revision 2.4 91/02/05 17:42:03 mrt 46 * Added author notices 47 * [91/02/04 11:14:23 mrt] 48 * 49 * Changed to use new Mach copyright 50 * [91/02/02 12:12:58 mrt] 51 * 52 * Revision 2.3 90/12/05 23:32:04 af 53 * 54 * 55 * Revision 2.1.1.2 90/11/01 02:48:10 af 56 * Reworked a bit, made reentrant. 57 * 58 * Revision 2.1.1.1 90/10/03 11:48:22 af 59 * Created, from the DEC specs: 60 * "DECstation 5000/200 KN02 System Module Functional Specification" 61 * Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990. 62 * [90/09/03 af] 63 */ 64 /* 65 * File: kn02.h 66 * Author: Alessandro Forin, Carnegie Mellon University 67 * Date: 9/90 68 * 69 * Definitions specific to the KN02 processor (3max) 70 */ 71 72 #ifndef MIPS_KN02_H 73 #define MIPS_KN02_H 1 74 75 /* 76 * KN02's Physical address space 77 */ 78 79 #define KN02_PHYS_MIN 0x00000000 /* 512 Meg */ 80 #define KN02_PHYS_MAX 0x1fffffff 81 82 /* 83 * Memory map 84 */ 85 86 #define KN02_PHYS_MEMORY_START 0x00000000 87 #define KN02_PHYS_MEMORY_END 0x1dffffff /* 480 Meg in 15 slots */ 88 89 /* 90 * I/O map 91 */ 92 93 #define KN02_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ 94 #define KN02_PHYS_TC_0_END 0x1e3fffff /* 4 Meg, option0 */ 95 96 #define KN02_PHYS_TC_1_START 0x1e400000 /* TURBOchannel, slot 1 */ 97 #define KN02_PHYS_TC_1_END 0x1e7fffff /* 4 Meg, option1 */ 98 99 #define KN02_PHYS_TC_2_START 0x1e800000 /* TURBOchannel, slot 2 */ 100 #define KN02_PHYS_TC_2_END 0x1ebfffff /* 4 Meg, option2 */ 101 102 #define KN02_PHYS_TC_3_START 0x1ec00000 /* TURBOchannel, slot 3 */ 103 #define KN02_PHYS_TC_3_END 0x1effffff /* 4 Meg, reserved*/ 104 105 #define KN02_PHYS_TC_4_START 0x1f000000 /* TURBOchannel, slot 4 */ 106 #define KN02_PHYS_TC_4_END 0x1f3fffff /* 4 Meg, reserved*/ 107 108 #define KN02_PHYS_TC_5_START 0x1f400000 /* TURBOchannel, slot 5 */ 109 #define KN02_PHYS_TC_5_END 0x1f7fffff /* 4 Meg, SCSI */ 110 111 #define KN02_PHYS_TC_6_START 0x1f800000 /* TURBOchannel, slot 6 */ 112 #define KN02_PHYS_TC_6_END 0x1fbfffff /* 4 Meg, ether */ 113 114 #define KN02_PHYS_TC_7_START 0x1fc00000 /* TURBOchannel, slot 7 */ 115 #define KN02_PHYS_TC_7_END 0x1fffffff /* 4 Meg, system devices */ 116 117 #define KN02_PHYS_TC_START KN02_PHYS_TC_0_START 118 #define KN02_PHYS_TC_END KN02_PHYS_TC_7_END /* 32 Meg */ 119 120 #define KN02_TC_NSLOTS 8 121 #define KN02_TC_MIN 0 122 #define KN02_TC_MAX 6 /* don't look at system slot */ 123 124 /* 125 * System devices 126 */ 127 128 #define KN02_SYS_ROM_START KN02_PHYS_TC_7_START+0x000000 129 #define KN02_SYS_ROM_END KN02_PHYS_TC_7_START+0x07ffff 130 131 #define KN02_SYS_RESERVED KN02_PHYS_TC_7_START+0x080000 132 133 #define KN02_SYS_CHKSYN KN02_PHYS_TC_7_START+0x100000 134 135 #define KN02_SYS_ERRADR KN02_PHYS_TC_7_START+0x180000 136 137 #define KN02_SYS_DZ KN02_PHYS_TC_7_START+0x200000 138 139 #define KN02_SYS_CLOCK KN02_PHYS_TC_7_START+0x280000 140 141 #define KN02_SYS_CSR KN02_PHYS_TC_7_START+0x300000 142 143 #define KN02_SYS_ROM1_START KN02_PHYS_TC_7_START+0x380000 144 #define KN02_SYS_ROM1_END KN02_PHYS_TC_7_START+0x3fffff 145 146 147 /* 148 * Interrupts 149 */ 150 151 #define KN02_INT_FPA IP_LEV7 /* Floating Point coproc */ 152 #define KN02_INT_RES1 IP_LEV6 /* reserved, unused */ 153 #define KN02_INT_MEM IP_LEV5 /* memory controller */ 154 #define KN02_INT_RES2 IP_LEV4 /* reserved, unused */ 155 #define KN02_INT_CLOCK IP_LEV3 /* rtc chip */ 156 #define KN02_INT_IO IP_LEV2 /* I/O slots */ 157 158 /* 159 * System board registers 160 */ 161 162 /* system Status and Control register */ 163 164 #define KN02_CSR_IOINT 0x000000ff /* ro */ 165 /* Interrupt pending */ 166 # define KN02_IP_DZ 0x00000080 /* serial lines */ 167 # define KN02_IP_LANCE 0x00000040 /* thin ethernet */ 168 # define KN02_IP_SCSI 0x00000020 /* ASC scsi controller */ 169 # define KN02_IP_XXXX 0x00000018 /* unused */ 170 # define KN02_IP_SLOT2 0x00000004 /* option slot 2 */ 171 # define KN02_IP_SLOT1 0x00000002 /* option slot 1 */ 172 # define KN02_IP_SLOT0 0x00000001 /* option slot 0 */ 173 174 #define KN02_CSR_BAUD38 0x00000100 /* rw */ 175 /* Max DZ baud rate */ 176 #define KN02_CSR_DIAGDN 0x00000200 /* rw */ 177 /* Diag jumper */ 178 #define KN02_CSR_BNK32M 0x00000400 /* rw */ 179 /* Memory bank stride */ 180 #define KN02_CSR_TXDIS 0x00000800 /* rw */ 181 /* Disable DZ xmit */ 182 #define KN02_CSR_LEDIAG 0x00001000 /* rw */ 183 /* Latch ECC */ 184 #define KN02_CSR_CORRECT 0x00002000 /* rw */ 185 /* ECC corrects single bit */ 186 #define KN02_CSR_ECCMD 0x0000c000 /* rw */ 187 /* ECC logic mode */ 188 #define KN02_CSR_IOINTEN 0x00ff0000 /* rw */ 189 #define KN02_CSR_IOINTEN_SHIFT 16 /* Interrupt enable */ 190 191 #define KN02_CSR_NRMMOD 0x01000000 /* ro */ 192 /* Diag jumper state */ 193 #define KN02_CSR_REFEVEN 0x02000000 /* ro */ 194 /* Refreshing even mem bank */ 195 #define KN02_CSR_PRSVNVR 0x04000000 /* ro */ 196 /* Preserve NVR jumper */ 197 #define KN02_CSR_PSWARN 0x08000000 /* ro */ 198 /* PS overheating */ 199 #define KN02_CSR_RRESERVED 0xf0000000 /* rz */ 200 201 #define KN02_CSR_LEDS 0x000000ff /* wo */ 202 /* Diag LEDs */ 203 #define KN02_CSR_WRESERVED 0xff000000 /* wz */ 204 205 206 /* Error address status register */ 207 208 #define KN02_ERR_ADDRESS 0x07ffffff /* phys address */ 209 #define KN02_ERR_RESERVED 0x08000000 /* unused */ 210 #define KN02_ERR_ECCERR 0x10000000 /* ECC error */ 211 #define KN02_ERR_WRITE 0x20000000 /* read/write transaction */ 212 #define KN02_ERR_CPU 0x40000000 /* CPU or device initiator */ 213 #define KN02_ERR_VALID 0x80000000 /* Info is valid */ 214 215 /* ECC check/syndrome status register */ 216 217 #define KN02_ECC_SYNLO 0x0000007f /* syndrome, even bank */ 218 #define KN02_ECC_SNGLO 0x00000080 /* single bit err, " */ 219 #define KN02_ECC_CHKLO 0x00007f00 /* check bits, " " */ 220 #define KN02_ECC_VLDLO 0x00008000 /* info valid for " */ 221 #define KN02_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ 222 #define KN02_ECC_SNGHI 0x00800000 /* single bit err, " */ 223 #define KN02_ECC_CHKHI 0x7f000000 /* check bits, " " */ 224 #define KN02_ECC_VLDHI 0x80000000 /* info valid for " */ 225 226 227 #endif /* MIPS_KN02_H */ 228