1 /*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * The Mach Operating System project at Carnegie-Mellon University, 7 * Ralph Campbell and Rick Macklem. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)kn03.h 8.1 (Berkeley) 06/10/93 12 */ 13 14 /* 15 * Mach Operating System 16 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 17 * All Rights Reserved. 18 * 19 * Permission to use, copy, modify and distribute this software and 20 * its documentation is hereby granted, provided that both the copyright 21 * notice and this permission notice appear in all copies of the 22 * software, derivative works or modified versions, and any portions 23 * thereof, and that both notices appear in supporting documentation. 24 * 25 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 26 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 27 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 28 * 29 * Carnegie Mellon requests users of this software to return to 30 * 31 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 32 * School of Computer Science 33 * Carnegie Mellon University 34 * Pittsburgh PA 15213-3890 35 * 36 * any improvements or extensions that they make and grant Carnegie the 37 * rights to redistribute these changes. 38 */ 39 /* 40 * Definitions specific to the KN03GA processors and 3MAX+ 41 * DECstation 5000/240 mother board. 42 */ 43 44 #ifndef MIPS_KN03_H 45 #define MIPS_KN03_H 1 46 47 /* 48 * 3MAX+'s Physical address space 49 */ 50 51 #define KN03_PHYS_MIN 0x00000000 /* 512 Meg */ 52 #define KN03_PHYS_MAX 0x1fffffff 53 54 /* 55 * Memory map 56 */ 57 58 #define KN03_PHYS_MEMORY_START 0x00000000 59 #define KN03_PHYS_MEMORY_END 0x1dffffff /* 480 Meg */ 60 61 /* 62 * I/O map 63 */ 64 65 #define KN03_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ 66 #define KN03_PHYS_TC_0_END 0x1e7fffff /* 8 Meg, option0 */ 67 68 #define KN03_PHYS_TC_1_START 0x1e800000 /* TURBOchannel, slot 1 */ 69 #define KN03_PHYS_TC_1_END 0x1effffff /* 8 Meg, option1 */ 70 71 #define KN03_PHYS_TC_2_START 0x1f000000 /* TURBOchannel, slot 2 */ 72 #define KN03_PHYS_TC_2_END 0x1f7fffff /* 8 Meg, option2 */ 73 74 #define KN03_PHYS_TC_3_START 0x1f800000 /* TURBOchannel, slot 3 */ 75 #define KN03_PHYS_TC_3_END 0x1fffffff /* 8 Meg, system devices */ 76 77 #define KN03_PHYS_TC_START KN03_PHYS_TC_0_START 78 #define KN03_PHYS_TC_END KN03_PHYS_TC_3_END 79 80 #define KN03_TC_NSLOTS 4 81 #define KN03_TC_MIN 0 82 #define KN03_TC_MAX 2 /* don't look at system slot */ 83 84 /* Pseudo-TCslots */ 85 #define KN03_SCSI_SLOT 3 86 #define KN03_LANCE_SLOT 4 87 #define KN03_SCC1_SLOT 5 88 #define KN03_SCC0_SLOT 6 89 #define KN03_ASIC_SLOT 7 90 91 /* 92 * System module space (IO ASIC) 93 */ 94 95 #define KN03_SYS_ASIC ( KN03_PHYS_TC_3_START + 0x0000000 ) 96 97 #define KN03_SYS_ROM_START ( KN03_SYS_ASIC + ASIC_SLOT_0_START ) 98 #define KN03_SYS_ASIC_REGS ( KN03_SYS_ASIC + ASIC_SLOT_1_START ) 99 #define KN03_SYS_ETHER_ADDRESS ( KN03_SYS_ASIC + ASIC_SLOT_2_START ) 100 #define KN03_SYS_LANCE ( KN03_SYS_ASIC + ASIC_SLOT_3_START ) 101 #define KN03_SYS_SCC_0 ( KN03_SYS_ASIC + ASIC_SLOT_4_START ) 102 #define KN03_SYS_SCC_1 ( KN03_SYS_ASIC + ASIC_SLOT_6_START ) 103 #define KN03_SYS_CLOCK ( KN03_SYS_ASIC + ASIC_SLOT_8_START ) 104 #define KN03_SYS_ERRADR ( KN03_SYS_ASIC + ASIC_SLOT_9_START ) 105 #define KN03_SYS_ERRSYN ( KN03_SYS_ASIC + ASIC_SLOT_10_START ) 106 #define KN03_SYS_CSR ( KN03_SYS_ASIC + ASIC_SLOT_11_START ) 107 #define KN03_SYS_SCSI ( KN03_SYS_ASIC + ASIC_SLOT_12_START ) 108 #define KN03_SYS_SCSI_DMA ( KN03_SYS_ASIC + ASIC_SLOT_14_START ) 109 #define KN03_SYS_BOOT_ROM_START ( KN03_PHYS_TC_3_START + 0x400000 ) 110 #define KN03_SYS_BOOT_ROM_END ( KN03_PHYS_TC_3_START + 0x43ffff ) 111 112 /* 113 * Interrupts 114 */ 115 116 #define KN03_INT_FPA IP_LEV7 /* Floating Point coproc */ 117 #define KN03_INT_HALTB IP_LEV6 /* Halt button */ 118 #define KN03_INT_MEM IP_LEV5 /* Memory Errors */ 119 #define KN03_INT_RTC IP_LEV3 /* RTC clock */ 120 #define KN03_INT_ASIC IP_LEV2 /* All turbochannel */ 121 122 #define KN03_REG_SCSI_DMAPTR ( KN03_SYS_ASIC + ASIC_SCSI_DMAPTR ) 123 #define KN03_REG_SCSI_DMANPTR ( KN03_SYS_ASIC + ASIC_SCSI_NEXTPTR ) 124 #define KN03_REG_LANCE_DMAPTR ( KN03_SYS_ASIC + ASIC_LANCE_DMAPTR ) 125 #define KN03_REG_SCC_T1_DMAPTR ( KN03_SYS_ASIC + ASIC_SCC_T1_DMAPTR ) 126 #define KN03_REG_SCC_R1_DMAPTR ( KN03_SYS_ASIC + ASIC_SCC_R1_DMAPTR ) 127 #define KN03_REG_SCC_T2_DMAPTR ( KN03_SYS_ASIC + ASIC_SCC_T2_DMAPTR ) 128 #define KN03_REG_SCC_R2_DMAPTR ( KN03_SYS_ASIC + ASIC_SCC_R2_DMAPTR ) 129 #define KN03_REG_CSR ( KN03_SYS_ASIC + ASIC_CSR ) 130 #define KN03_REG_INTR ( KN03_SYS_ASIC + ASIC_INTR ) 131 #define KN03_REG_IMSK ( KN03_SYS_ASIC + ASIC_IMSK ) 132 #define KN03_REG_CURADDR ( KN03_SYS_ASIC + ASIC_CURADDR ) 133 134 #define KN03_REG_LANCE_DECODE ( KN03_SYS_ASIC + ASIC_LANCE_DECODE ) 135 #define KN03_REG_SCSI_DECODE ( KN03_SYS_ASIC + ASIC_SCSI_DECODE ) 136 #define KN03_REG_SCC0_DECODE ( KN03_SYS_ASIC + ASIC_SCC0_DECODE ) 137 #define KN03_REG_SCC1_DECODE ( KN03_SYS_ASIC + ASIC_SCC1_DECODE ) 138 # define KN03_LANCE_CONFIG 3 139 # define KN03_SCSI_CONFIG 14 140 # define KN03_SCC0_CONFIG (0x10|4) 141 # define KN03_SCC1_CONFIG (0x10|6) 142 143 #define KN03_REG_SCSI_SCR ( KN03_SYS_ASIC + ASIC_SCSI_SCR ) 144 #define KN03_REG_SCSI_SDR0 ( KN03_SYS_ASIC + ASIC_SCSI_SDR0 ) 145 #define KN03_REG_SCSI_SDR1 ( KN03_SYS_ASIC + ASIC_SCSI_SDR1 ) 146 147 /* NOTES 148 149 Memory access priority is, from higher to lower: 150 - DRAM refresh 151 - IO DMA (IO Control ASIC) 152 - Slot 2 DMA 153 - Slot 1 DMA 154 - Slot 0 DMA 155 - Processor 156 157 */ 158 159 /* 160 * More system registers defines (IO Control ASIC) 161 */ 162 163 /* (re)defines for the system Status and Control register (SSR) */ 164 165 #define KN03_CSR_DMAEN_T1 ASIC_CSR_DMAEN_T1 166 #define KN03_CSR_DMAEN_R1 ASIC_CSR_DMAEN_R1 167 #define KN03_CSR_DMAEN_T2 ASIC_CSR_DMAEN_T2 168 #define KN03_CSR_DMAEN_R2 ASIC_CSR_DMAEN_R2 169 #define KN03_CSR_SCSI_DIR ASIC_CSR_SCSI_DIR 170 #define KN03_CSR_DMAEN_SCSI ASIC_CSR_DMAEN_SCSI 171 #define KN03_CSR_DMAEN_LANCE ASIC_CSR_DMAEN_LANCE 172 #define KN03_CSR_DIAGDN 0x00008000 /* rw */ 173 #define KN03_CSR_TXDIS_2 0x00004000 /* rw */ 174 #define KN03_CSR_TXDIS_1 0x00002000 /* rw */ 175 #define KN03_CSR_SCC_ENABLE 0x00000800 /* rw */ 176 #define KN03_CSR_RTC_ENABLE 0x00000400 /* rw */ 177 #define KN03_CSR_SCSI_ENABLE 0x00000200 /* rw */ 178 #define KN03_CSR_LANCE_ENABLE 0x00000100 /* rw */ 179 #define KN03_CSR_LEDS 0x000000ff /* rw */ 180 181 /* (re)defines for the System Interrupt and Mask Registers */ 182 183 #define KN03_INTR_T1_PAGE_END ASIC_INTR_T1_PAGE_END 184 #define KN03_INTR_T1_READ_E ASIC_INTR_T1_READ_E 185 #define KN03_INTR_R1_HALF_PAGE ASIC_INTR_R1_HALF_PAGE 186 #define KN03_INTR_R1_DMA_OVRUN ASIC_INTR_R1_DMA_OVRUN 187 #define KN03_INTR_T2_PAGE_END ASIC_INTR_T2_PAGE_END 188 #define KN03_INTR_T2_READ_E ASIC_INTR_T2_READ_E 189 #define KN03_INTR_R2_HALF_PAGE ASIC_INTR_R2_HALF_PAGE 190 #define KN03_INTR_R2_DMA_OVRUN ASIC_INTR_R2_DMA_OVRUN 191 #define KN03_INTR_SCSI_PTR_LOAD ASIC_INTR_SCSI_PTR_LOAD 192 #define KN03_INTR_SCSI_OVRUN ASIC_INTR_SCSI_OVRUN 193 #define KN03_INTR_SCSI_READ_E ASIC_INTR_SCSI_READ_E 194 #define KN03_INTR_LANCE_READ_E ASIC_INTR_LANCE_READ_E 195 #define KN03_INTR_NVR_JUMPER 0x00004000 /* ro */ 196 #define KN03_INTR_TC_2 0x00002000 /* ro */ 197 #define KN03_INTR_TC_1 0x00001000 /* ro */ 198 #define KN03_INTR_TC_0 0x00000800 /* ro */ 199 #define KN03_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 200 #define KN03_INTR_SCSI 0x00000200 /* ro */ 201 #define KN03_INTR_LANCE 0x00000100 /* ro */ 202 #define KN03_INTR_SCC_1 0x00000080 /* ro */ 203 #define KN03_INTR_SCC_0 0x00000040 /* ro */ 204 #define KN03_INTR_CLOCK 0x00000020 /* ro */ 205 #define KN03_INTR_PSWARN 0x00000010 /* ro */ 206 #define KN03_INTR_SCSI_FIFO 0x00000004 /* ro */ 207 #define KN03_INTR_PBNC 0x00000002 /* ro */ 208 #define KN03_INTR_PBNO 0x00000001 /* ro */ 209 #define KN03_INTR_ASIC 0xff0f0004 210 #define KN03_IM0 0xff0f3bf0 /* all good ones enabled */ 211 212 /* 213 * XXX I made a wild guess this register looks the same as for the KN02. 214 */ 215 216 #define KN03_ERR_ADDRESS 0x07ffffff /* phys address */ 217 #define KN03_ERR_RESERVED 0x08000000 /* unused */ 218 #define KN03_ERR_ECCERR 0x10000000 /* ECC error */ 219 #define KN03_ERR_WRITE 0x20000000 /* read/write transaction */ 220 #define KN03_ERR_CPU 0x40000000 /* CPU or device initiator */ 221 #define KN03_ERR_VALID 0x80000000 /* Info is valid */ 222 223 /* ECC check/syndrome status register */ 224 225 #define KN03_ECC_SYNLO 0x0000007f /* syndrome, even bank */ 226 #define KN03_ECC_SNGLO 0x00000080 /* single bit err, " */ 227 #define KN03_ECC_CHKLO 0x00007f00 /* check bits, " " */ 228 #define KN03_ECC_VLDLO 0x00008000 /* info valid for " */ 229 #define KN03_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ 230 #define KN03_ECC_SNGHI 0x00800000 /* single bit err, " */ 231 #define KN03_ECC_CHKHI 0x7f000000 /* check bits, " " */ 232 #define KN03_ECC_VLDHI 0x80000000 /* info valid for " */ 233 #endif /* MIPS_KN03_H */ 234