1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)bsd_audioreg.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: bsd_audioreg.h,v 1.3 92/06/07 21:12:50 mccanne Exp $ (LBL) 19 */ 20 21 /* 22 * Bit encodings for chip commands from "Microprocessor Access Guide for 23 * Indirect Registers", p.19 Am79C30A/32A Advanced Micro Devices spec 24 * sheet (preliminary). 25 * 26 * Indirect register numbers (the value written into cr to select a given 27 * chip registers) have the form AMDR_*. Register fields look like AMD_*. 28 */ 29 30 struct amd7930 { 31 u_char cr; /* command register (wo) */ 32 #define ir cr /* interrupt register (ro) */ 33 u_char dr; /* data register (rw) */ 34 u_char dsr1; /* D-channel status register 1 (ro) */ 35 u_char der; /* D-channel error register (ro) */ 36 u_char dctb; /* D-channel transmit register (wo) */ 37 #define dcrb dctb /* D-channel receive register (ro) */ 38 u_char bbtb; /* Bb-channel transmit register (wo) */ 39 #define bbrb bbtb /* Bb-channel receive register (ro) */ 40 u_char bctb; /* Bc-channel transmit register (wo) */ 41 #define bcrb bctb /* Bc-channel receive register (ro) */ 42 u_char dsr2; /* D-channel status register 2 (ro) */ 43 }; 44 45 #define AMDR_INIT 0x21 46 #define AMD_INIT_PMS_IDLE 0x00 47 #define AMD_INIT_PMS_ACTIVE 0x01 48 #define AMD_INIT_PMS_ACTIVE_DATA 0x02 49 #define AMD_INIT_INT_DISABLE (0x01 << 2) 50 #define AMD_INIT_CDS_DIV2 (0x00 << 3) 51 #define AMD_INIT_CDS_DIV1 (0x01 << 3) 52 #define AMD_INIT_CDS_DIV4 (0x02 << 3) 53 #define AMD_INIT_AS_RX (0x01 << 6) 54 #define AMD_INIT_AS_TX (0x01 << 7) 55 56 #define AMDR_LIU_LSR 0xa1 57 #define AMDR_LIU_LPR 0xa2 58 #define AMDR_LIU_LMR1 0xa3 59 #define AMDR_LIU_LMR2 0xa4 60 #define AMDR_LIU_2_4 0xa5 61 #define AMDR_LIU_MF 0xa6 62 #define AMDR_LIU_MFSB 0xa7 63 #define AMDR_LIU_MFQB 0xa8 64 65 #define AMDR_MUX_MCR1 0x41 66 #define AMDR_MUX_MCR2 0x42 67 #define AMDR_MUX_MCR3 0x43 68 #define AMD_MCRCHAN_NC 0x00 69 #define AMD_MCRCHAN_B1 0x01 70 #define AMD_MCRCHAN_B2 0x02 71 #define AMD_MCRCHAN_BA 0x03 72 #define AMD_MCRCHAN_BB 0x04 73 #define AMD_MCRCHAN_BC 0x05 74 #define AMD_MCRCHAN_BD 0x06 75 #define AMD_MCRCHAN_BE 0x07 76 #define AMD_MCRCHAN_BF 0x08 77 #define AMDR_MUX_MCR4 0x44 78 #define AMD_MCR4_INT_ENABLE (1 << 3) 79 #define AMD_MCR4_SWAPBB (1 << 4) 80 #define AMD_MCR4_SWAPBC (1 << 5) 81 82 #define AMDR_MUX_1_4 0x45 83 84 #define AMDR_MAP_X 0x61 85 #define AMDR_MAP_R 0x62 86 #define AMDR_MAP_GX 0x63 87 #define AMDR_MAP_GR 0x64 88 #define AMDR_MAP_GER 0x65 89 #define AMDR_MAP_STG 0x66 90 #define AMDR_MAP_FTGR 0x67 91 #define AMDR_MAP_ATGR 0x68 92 #define AMDR_MAP_MMR1 0x69 93 #define AMD_MMR1_ALAW 0x01 94 #define AMD_MMR1_GX 0x02 95 #define AMD_MMR1_GR 0x04 96 #define AMD_MMR1_GER 0x08 97 #define AMD_MMR1_X 0x10 98 #define AMD_MMR1_R 0x20 99 #define AMD_MMR1_STG 0x40 100 #define AMD_MMR1_LOOP 0x80 101 #define AMDR_MAP_MMR2 0x6a 102 #define AMD_MMR2_AINB 0x01 103 #define AMD_MMR2_LS 0x02 104 #define AMD_MMR2_DTMF 0x04 105 #define AMD_MMR2_GEN 0x08 106 #define AMD_MMR2_RNG 0x10 107 #define AMD_MMR2_DIS_HPF 0x20 108 #define AMD_MMR2_DIS_AZ 0x40 109 #define AMDR_MAP_1_10 0x6b 110 111 #define AMDR_DLC_FRAR123 0x81 112 #define AMDR_DLC_SRAR123 0x82 113 #define AMDR_DLC_TAR 0x83 114 #define AMDR_DLC_DRLR 0x84 115 #define AMDR_DLC_DTCR 0x85 116 #define AMDR_DLC_DMR1 0x86 117 #define AMDR_DLC_DMR2 0x87 118 #define AMDR_DLC_1_7 0x88 119 #define AMDR_DLC_DRCR 0x89 120 #define AMDR_DLC_RNGR1 0x8a 121 #define AMDR_DLC_RNGR2 0x8b 122 #define AMDR_DLC_FRAR4 0x8c 123 #define AMDR_DLC_SRAR4 0x8d 124 #define AMDR_DLC_DMR3 0x8e 125 #define AMDR_DLC_DMR4 0x8f 126 #define AMDR_DLC_12_15 0x90 127 #define AMDR_DLC_ASR 0x91 128