1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)zsreg.h 7.3 (Berkeley) 04/20/93 17 * 18 * from: $Header: zsreg.h,v 1.7 92/11/26 01:27:18 torek Exp $ (LBL) 19 */ 20 21 /* 22 * Zilog SCC registers, as implemented on the Sun-4c. 23 * 24 * Each Z8530 implements two channels (called `a' and `b'). 25 * 26 * The damnable chip was designed to fit on Z80 I/O ports, and thus 27 * has everything multiplexed out the wazoo. We have to select 28 * a register, then read or write the register, and so on. Worse, 29 * the parameter bits are scattered all over the register space. 30 * This thing is full of `miscellaneous' control registers. 31 * 32 * Worse yet, the registers have incompatible functions on read 33 * and write operations. We describe the registers below according 34 * to whether they are `read registers' (RR) or `write registers' (WR). 35 * As if this were not enough, some of the channel B status bits show 36 * up in channel A, and vice versa. The blasted thing shares write 37 * registers 2 and 9 across both channels, and reads registers 2 and 3 38 * differently for the two channels. We can, however, ignore this much 39 * of the time. 40 */ 41 #ifndef LOCORE 42 struct zschan { 43 u_char zc_csr; /* control and status, and indirect access */ 44 u_char zc_xxx0; 45 u_char zc_data; /* data */ 46 u_char zc_xxx1; 47 }; 48 49 /* 50 * N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya 51 * is 0. In other words, the things are BACKWARDS. 52 */ 53 struct zsdevice { 54 struct zschan zs_chan[2]; /* channel A = 1, B = 0 */ 55 }; 56 57 #define CHAN_A 1 58 #define CHAN_B 0 59 #endif 60 61 /* 62 * Some of the names in this files were chosen to make the hsis driver 63 * work unchanged (which means that they will match some in SunOS). 64 * 65 * `S.C.' stands for Special Condition, which is any of these: 66 * receiver overrun (aka silo overflow) 67 * framing error (missing stop bit, etc) 68 * end of frame (in synchronous modes) 69 * parity error (when `parity error is S.C.' is set) 70 */ 71 72 /* 73 * Registers with only a single `numeric value' get a name. 74 * Other registers hold bits and are only numbered; the bit 75 * definitions imply the register number (see below). 76 * 77 * We never use the receive and transmit data registers as 78 * indirects (choosing instead the zc_data register), so they 79 * are not defined here. 80 */ 81 #define ZSRR_IVEC 2 /* interrupt vector (channel 0) */ 82 #define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ 83 #define ZSRR_BAUDLO 12 /* baud rate generator (low half) */ 84 #define ZSRR_BAUDHI 13 /* baud rate generator (high half) */ 85 86 #define ZSWR_IVEC 2 /* interrupt vector (shared) */ 87 #define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ 88 #define ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */ 89 #define ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */ 90 #define ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */ 91 #define ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ 92 #define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ 93 #define ZSWR_BAUDLO 12 /* baud rate generator (low half) */ 94 #define ZSWR_BAUDHI 13 /* baud rate generator (high half) */ 95 96 /* 97 * Registers 0 through 7 may be written with any one of the 8 command 98 * modifiers, and/or any one of the 4 reset modifiers, defined below. 99 * To write registers 8 through 15, however, the command modifier must 100 * always be `point high'. Rather than track this bizzareness all over 101 * the driver, we try to avoid using any modifiers, ever (but they are 102 * defined here if you want them). 103 */ 104 #define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */ 105 #define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */ 106 #define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */ 107 #define ZSM_NULL 0x00 /* nothing special */ 108 109 #define ZSM_RESET_IUS 0x38 /* reset interrupt under service */ 110 #define ZSM_RESET_ERR 0x30 /* reset error cond */ 111 #define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */ 112 #define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */ 113 #define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */ 114 #define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */ 115 #define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */ 116 #define ZSM_NULL 0x00 /* nothing special */ 117 118 /* 119 * Commands for Write Register 0 (`Command Register'). 120 * These are just the command modifiers or'ed with register number 0 121 * (which of course equals the command modifier). 122 */ 123 #define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM 124 #define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC 125 #define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC 126 #define ZSWR0_CLR_INTR ZSM_RESET_IUS 127 #define ZSWR0_RESET_ERRORS ZSM_RESET_ERR 128 #define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC 129 #define ZSWR0_SEND_ABORT ZSM_SEND_ABORT 130 #define ZSWR0_RESET_STATUS ZSM_RESET_STINT 131 #define ZSWR0_RESET_TXINT ZSM_RESET_TXINT 132 133 /* 134 * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data 135 * Transfer Mode Definition'). Note that bits 3 and 4 are taken together 136 * as a single unit, and bits 5 and 6 are useful only if bit 7 is set. 137 */ 138 #define ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */ 139 #define ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */ 140 #define ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */ 141 #define ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */ 142 143 #define ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */ 144 #define ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */ 145 #define ZSWR1_RIE 0x10 /* rxint per char & on S.C. */ 146 #define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */ 147 148 #define ZSWR1_PE_SC 0x04 /* parity error is special condition */ 149 #define ZSWR1_TIE 0x02 /* transmit interrupt enable */ 150 #define ZSWR1_SIE 0x01 /* external/status interrupt enable */ 151 152 /* HSIS compat */ 153 #define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX) 154 155 /* 156 * Bits in Write Register 3 (`Receive Parameters and Control'). 157 * Bits 7 and 6 are taken as a unit. Note that the receive bits 158 * per character ordering is insane. 159 * 160 * Here `hardware flow control' means CTS enables the transmitter 161 * and DCD enables the receiver. The latter is neither interesting 162 * nor useful, and gets in our way, making it almost unusable. 163 */ 164 #define ZSWR3_RX_5 0x00 /* receive 5 bits per char */ 165 #define ZSWR3_RX_7 0x40 /* receive 7 bits per char */ 166 #define ZSWR3_RX_6 0x80 /* receive 6 bits per char */ 167 #define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ 168 169 #define ZSWR3_HFC 0x20 /* hardware flow control */ 170 #define ZSWR3_HUNT 0x10 /* enter hunt mode */ 171 #define ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */ 172 #define ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */ 173 #define ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */ 174 #define ZSWR3_RX_ENABLE 0x01 /* receiver enable */ 175 176 /* 177 * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters 178 * and Modes'). Bits 7&6, 5&4, and 3&2 are taken as units. 179 */ 180 #define ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */ 181 #define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ 182 #define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ 183 #define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ 184 185 #define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ 186 #define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ 187 #define ZSWR4_SDLC 0x20 /* SDLC mode */ 188 #define ZSWR4_EXTSYNC 0x30 /* external sync mode */ 189 190 #define ZSWR4_SYNCMODE 0x00 /* one of the above sync modes */ 191 #define ZSWR4_ONESB 0x04 /* 1 stop bit */ 192 #define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ 193 #define ZSWR4_TWOSB 0x0c /* 2 stop bits */ 194 195 #define ZSWR4_EVENP 0x02 /* check for even parity */ 196 #define ZSWR4_PARENB 0x01 /* enable parity checking */ 197 198 /* 199 * Bits in Write Register 5 (`Transmit Parameter and Controls'). 200 * Bits 6 and 5 are taken as a unit; the ordering is, as with RX 201 * bits per char, not sensible. 202 */ 203 #define ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */ 204 205 #define ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */ 206 #define ZSWR5_TX_7 0x20 /* transmit 7 bits */ 207 #define ZSWR5_TX_6 0x40 /* transmit 6 bits */ 208 #define ZSWR5_TX_8 0x60 /* transmit 8 bits */ 209 210 #define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ 211 #define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ 212 #define ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */ 213 #define ZSWR5_RTS 0x02 /* assert RTS */ 214 #define ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */ 215 216 #ifdef not_done_here 217 /* 218 * Bits in Write Register 7 when the chip is in SDLC mode. 219 */ 220 #define ZSWR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */ 221 #endif 222 223 /* 224 * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6 225 * are taken as a unit and indicate the type of reset; 00 means no reset 226 * (and is not defined here). 227 */ 228 #define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ 229 #define ZSWR9_A_RESET 0x80 /* reset channel A (0) */ 230 #define ZSWR9_B_RESET 0x40 /* reset channel B (1) */ 231 /* 0x20 unused */ 232 233 #define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ 234 #define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ 235 #define ZSWR9_DLC 0x04 /* disable lower chain */ 236 #define ZSWR9_NO_VECTOR 0x02 /* no vector */ 237 #define ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */ 238 239 /* 240 * Bits in Write Register 10 (`Miscellaneous Transmitter/Receiver Control 241 * Bits'). Bits 6 & 5 are taken as a unit, and some of the bits are 242 * meaningful only in certain modes. Bleah. 243 */ 244 #define ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */ 245 246 #define ZSWR10_NRZ 0x00 /* NRZ encoding */ 247 #define ZSWR10_NRZI 0x20 /* NRZI encoding */ 248 #define ZSWR10_FM1 0x40 /* FM1 encoding */ 249 #define ZSWR10_FM0 0x60 /* FM0 encoding */ 250 251 #define ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */ 252 #define ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */ 253 #define ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */ 254 #define ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */ 255 #define ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */ 256 257 /* 258 * Bits in Write Register 11 (`Clock Mode Control'). Bits 6&5, 4&3, and 259 * 1&0 are taken as units. Various bits depend on other bits in complex 260 * ways; see the Zilog manual. 261 */ 262 #define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ 263 /* (else have TTL oscil. on RTxC*) */ 264 #define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from TRxC* pin */ 265 #define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ 266 #define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ 267 #define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ 268 269 #define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from TRxC* pin */ 270 #define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from RTxC* pin */ 271 #define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ 272 #define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ 273 274 #define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */ 275 /* (unless it is being used above) */ 276 #define ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */ 277 #define ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */ 278 #define ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */ 279 #define ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */ 280 281 /* 282 * Formula for Write Registers 12 and 13 (`Lower Byte of Baud Rate 283 * Generator Time Constant' and `Upper Byte of ...'). Inputs: 284 * 285 * f BRG input clock frequency (in Hz) AFTER division 286 * by 1, 16, 32, or 64 (per clock divisor in WR4) 287 * bps desired rate in bits per second (9600, etc) 288 * 289 * We want 290 * 291 * f 292 * ----- + 0.5 - 2 293 * 2 bps 294 * 295 * rounded down to an integer. This can be computed entirely 296 * in integer arithemtic as: 297 * 298 * f + bps 299 * ------- - 2 300 * 2 bps 301 */ 302 #define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2) 303 304 /* inverse of above: given a BRG Time Constant, return Bits Per Second */ 305 #define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2)) 306 307 /* 308 * Bits in Write Register 14 (`Miscellaneous Control Bits'). 309 * Bits 7 through 5 are taken as a unit and make up a `DPLL command'. 310 */ 311 #define ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */ 312 #define ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */ 313 #define ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */ 314 #define ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */ 315 #define ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */ 316 #define ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */ 317 #define ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */ 318 #define ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */ 319 320 #define ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */ 321 #define ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */ 322 #define ZSWR14_DTR_REQ 0x04 /* DTR*/REQ* pin gives REQ* */ 323 #define ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */ 324 /* (else from RTxC* pin or xtal osc) */ 325 #define ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */ 326 327 /* 328 * Bits in Write Register 15 (`External/Status Interrupt Control'). 329 * Most of these cause status interrupts whenever the corresponding 330 * bit or pin changes state (i.e., any rising or falling edge). 331 */ 332 #define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ 333 #define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ 334 #define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ 335 #define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ 336 #define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ 337 /* 0x04 unused, must be zero */ 338 #define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ 339 /* 0x01 unused, must be zero */ 340 341 /* 342 * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External 343 * Status'). 344 */ 345 #define ZSRR0_BREAK 0x80 /* break/abort detected */ 346 #define ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */ 347 #define ZSRR0_CTS 0x20 /* clear to send */ 348 #define ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */ 349 #define ZSRR0_DCD 0x08 /* data carrier detect */ 350 #define ZSRR0_TX_READY 0x04 /* transmit buffer empty */ 351 #define ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */ 352 #define ZSRR0_RX_READY 0x01 /* received character ready */ 353 354 /* 355 * Bits in Read Register 1 (the Zilog book does not name this one). 356 */ 357 #define ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */ 358 #define ZSRR1_FE 0x40 /* CRC/framing error */ 359 #define ZSRR1_DO 0x20 /* data (receiver) overrun */ 360 #define ZSRR1_PE 0x10 /* parity error */ 361 #define ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */ 362 #define ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */ 363 #define ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */ 364 #define ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */ 365 366 /* 367 * Read Register 2 in B channel contains status bits if VECTOR_INCL_STAT 368 * is set. 369 */ 370 371 /* 372 * Bits in Read Register 3 (`Interrupt Pending'). Only channel A 373 * has an RR3. 374 */ 375 /* 0x80 unused, returned as 0 */ 376 /* 0x40 unused, returned as 0 */ 377 #define ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */ 378 #define ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */ 379 #define ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */ 380 #define ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */ 381 #define ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */ 382 #define ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */ 383 384 /* 385 * Bits in Read Register 10 (`contains some miscellaneous status bits'). 386 */ 387 #define ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */ 388 #define ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */ 389 /* 0x20 unused */ 390 #define ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */ 391 /* 0x08 unused */ 392 /* 0x04 unused */ 393 #define ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */ 394 395 /* 396 * Bits in Read Register 15. This register is one of the few that 397 * simply reads back the corresponding Write Register. 398 */ 399 #define ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */ 400 #define ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */ 401 #define ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */ 402 #define ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */ 403 #define ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */ 404 /* 0x04 unused, returned as zero */ 405 #define ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */ 406 /* 0x01 unused, returned as zero */ 407