1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratories. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)zsvar.h 7.2 (Berkeley) 07/21/92 17 * 18 * from: $Header: zsvar.h,v 1.4 92/06/17 05:35:54 torek Exp $ (LBL) 19 */ 20 21 /* 22 * Software state, per zs channel. 23 * 24 * The receive ring size and type are carefully chosen to make the 25 * zs hardware interrupt handler go fast. We need 8 bits for the 26 * received character and 8 bits for the corresponding RR1 status. 27 * The character is known to be in the upper byte of the pair. 28 */ 29 #define ZLRB_RING_SIZE 256 30 #define ZLRB_RING_MASK 255 31 32 struct zs_chanstate { 33 struct zs_chanstate *cs_next; /* linked list for zshard() */ 34 volatile struct zschan *cs_zc; /* points to hardware regs */ 35 int cs_unit; /* unit number */ 36 struct tty *cs_ttyp; /* ### */ 37 38 /* 39 * We must keep a copy of the write registers as they are 40 * mostly write-only and we sometimes need to set and clear 41 * individual bits (e.g., in WR3). Not all of these are 42 * needed but 16 bytes is cheap and this makes the addressing 43 * simpler. Unfortunately, we can only write to some registers 44 * when the chip is not actually transmitting, so whenever 45 * we are expecting a `transmit done' interrupt the wreg array 46 * is allowed to `get ahead' of the current values. In a 47 * few places we must change the current value of a register, 48 * rather than (or in addition to) the pending value; for these 49 * cs_creg[] contains the current value. 50 */ 51 u_char cs_creg[16]; /* current values */ 52 u_char cs_preg[16]; /* pending values */ 53 u_char cs_heldchange; /* change pending (creg != preg) */ 54 55 /* 56 * The transmit byte count and address are used for pseudo-DMA 57 * output in the hardware interrupt code. PDMA can be suspended 58 * to get pending changes done; heldtbc is used for this. It can 59 * also be stopped for ^S; this sets TS_TTSTOP in tp->t_state. 60 */ 61 int cs_tbc; /* transmit byte count */ 62 caddr_t cs_tba; /* transmit buffer address */ 63 int cs_heldtbc; /* held tbc while xmission stopped */ 64 65 /* 66 * Printing an overrun error message often takes long enough to 67 * cause another overrun, so we only print one per second. 68 */ 69 long cs_rotime; /* time of last ring overrun */ 70 long cs_fotime; /* time of last fifo overrun */ 71 72 /* pure software data, per channel */ 73 int cs_speed; /* default baud rate (from ROM) */ 74 char cs_softcar; /* software carrier */ 75 char cs_conk; /* is console keyboard, decode L1-A */ 76 char cs_brkabort; /* abort (as if via L1-A) on BREAK */ 77 char cs_kgdb; /* enter debugger on frame char */ 78 char cs_consio; /* port does /dev/console I/O */ 79 80 /* 81 * Status change interrupts merely copy the new status and 82 * schedule a software interrupt to deal with it. To make 83 * checking easier, cs_rr0 is guaranteed nonzero on status 84 * changes. cs_txint indicates a software transmit interrupt 85 * (a txint where cs_tbc was 0). A software receive interrupt 86 * is implicit in cs_rbget != cs_rbput. 87 */ 88 u_char cs_txint; /* software tx interrupt */ 89 u_short cs_rr0; /* rr0 | 0x100, after change */ 90 u_int cs_rbget; /* receive ring buffer `get' index */ 91 volatile u_int cs_rbput; /* receive ring buffer `put' index */ 92 u_short cs_rbuf[ZLRB_RING_SIZE];/* packed data: (char << 8) + rr1 */ 93 }; 94 95 /* 96 * Macros to read and write individual registers (except 0) in a channel. 97 * 98 * On the SparcStation the 1.6 microsecond recovery time is 99 * handled in hardware. 100 */ 101 #define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr) 102 #define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v)) 103