1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)fpu_emu.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: fpu_emu.h,v 1.3 92/11/26 01:30:54 torek Exp $ 19 */ 20 21 /* 22 * Floating point emulator (tailored for SPARC, but structurally 23 * machine-independent). 24 * 25 * Floating point numbers are carried around internally in an `expanded' 26 * or `unpacked' form consisting of: 27 * - sign 28 * - unbiased exponent 29 * - mantissa (`1.' + 112-bit fraction + guard + round) 30 * - sticky bit 31 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 32 * always nonzero. Additional low-order `guard' and `round' bits are 33 * scrunched in, making the entire mantissa 115 bits long. This is divided 34 * into four 32-bit words, with `spare' bits left over in the upper part 35 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 36 * number is thus kept within the half-open interval [1.0,2.0) (but see 37 * the `number classes' below). This holds even for denormalized numbers: 38 * when we explode an external denorm, we normalize it, introducing low-order 39 * zero bits, so that the rest of the code always sees normalized values. 40 * 41 * Note that a number of our algorithms use the `spare' bits at the top. 42 * The most demanding algorithm---the one for sqrt---depends on two such 43 * bits, so that it can represent values up to (but not including) 8.0, 44 * and then it needs a carry on top of that, so that we need three `spares'. 45 * 46 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 47 * whole words from the mantissa into it. 48 * 49 * All operations are done in this internal extended precision. According 50 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 51 * it is OK to do a+b in extended precision and then round the result to 52 * single precision---provided single, double, and extended precisions are 53 * `far enough apart' (they always are), but we will try to avoid any such 54 * extra work where possible. 55 */ 56 struct fpn { 57 int fp_class; /* see below */ 58 int fp_sign; /* 0 => positive, 1 => negative */ 59 int fp_exp; /* exponent (unbiased) */ 60 int fp_sticky; /* nonzero bits lost at right end */ 61 u_int fp_mant[4]; /* 115-bit mantissa */ 62 }; 63 64 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 65 #define FP_NG 2 /* number of low-order guard bits */ 66 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 67 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 68 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 69 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 70 71 /* 72 * Number classes. Since zero, Inf, and NaN cannot be represented using 73 * the above layout, we distinguish these from other numbers via a class. 74 * In addition, to make computation easier and to follow Appendix N of 75 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 76 */ 77 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 78 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 79 #define FPC_ZERO 0 /* zero (sign matters) */ 80 #define FPC_NUM 1 /* number (sign matters) */ 81 #define FPC_INF 2 /* infinity (sign matters) */ 82 83 #define ISNAN(fp) ((fp)->fp_class < 0) 84 #define ISZERO(fp) ((fp)->fp_class == 0) 85 #define ISINF(fp) ((fp)->fp_class == FPC_INF) 86 87 /* 88 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 89 * to the `more significant' operand for our purposes. Appendix N says that 90 * the result of a computation involving two numbers are: 91 * 92 * If both are SNaN: operand 2, converted to Quiet 93 * If only one is SNaN: the SNaN operand, converted to Quiet 94 * If both are QNaN: operand 2 95 * If only one is QNaN: the QNaN operand 96 * 97 * In addition, in operations with an Inf operand, the result is usually 98 * Inf. The class numbers are carefully arranged so that if 99 * (unsigned)class(op1) > (unsigned)class(op2) 100 * then op1 is the one we want; otherwise op2 is the one we want. 101 */ 102 #define ORDER(x, y) { \ 103 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 104 SWAP(x, y); \ 105 } 106 #define SWAP(x, y) { \ 107 register struct fpn *swap; \ 108 swap = (x), (x) = (y), (y) = swap; \ 109 } 110 111 /* 112 * Emulator state. 113 */ 114 struct fpemu { 115 struct fpstate *fe_fpstate; /* registers, etc */ 116 int fe_fsr; /* fsr copy (modified during op) */ 117 int fe_cx; /* exceptions */ 118 struct fpn fe_f1; /* operand 1 */ 119 struct fpn fe_f2; /* operand 2, if required */ 120 struct fpn fe_f3; /* available storage for result */ 121 }; 122 123 /* 124 * Arithmetic functions. 125 * Each of these may modify its inputs (f1,f2) and/or the temporary. 126 * Each returns a pointer to the result and/or sets exceptions. 127 */ 128 struct fpn *fpu_add(struct fpemu *); 129 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe)) 130 struct fpn *fpu_mul(struct fpemu *); 131 struct fpn *fpu_div(struct fpemu *); 132 struct fpn *fpu_sqrt(struct fpemu *); 133 134 /* 135 * Other functions. 136 */ 137 138 /* Perform a compare instruction (with or without unordered exception). */ 139 void fpu_compare(struct fpemu *, int); 140 141 /* Build a new Quiet NaN (sign=0, frac=all 1's). */ 142 struct fpn *fpu_newnan(struct fpemu *); 143 144 /* 145 * Shift a number right some number of bits, taking care of round/sticky. 146 * Note that the result is probably not a well-formed number (it will lack 147 * the normal 1-bit mant[0]&FP_1). 148 */ 149 int fpu_shr(struct fpn *, int); 150 151 /* Conversion to and from internal format -- note asymmetry. */ 152 int fpu_itofpn(struct fpn *, u_int); 153 int fpu_stofpn(struct fpn *, u_int); 154 int fpu_dtofpn(struct fpn *, u_int, u_int); 155 int fpu_xtofpn(struct fpn *, u_int, u_int, u_int, u_int); 156 157 u_int fpu_fpntoi(struct fpemu *, struct fpn *); 158 u_int fpu_fpntos(struct fpemu *, struct fpn *); 159 u_int fpu_fpntod(struct fpemu *, struct fpn *); 160 u_int fpu_fpntox(struct fpemu *, struct fpn *); 161 162 void fpu_explode(struct fpemu *, struct fpn *, int, int); 163 void fpu_implode(struct fpemu *, struct fpn *, int, u_int *); 164