1 /* 2 * Copyright (c) 1992 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * %sccs.include.redist.c% 10 * 11 * @(#)ctlreg.h 7.1 (Berkeley) 07/13/92 12 * 13 * from: $Header: ctlreg.h,v 1.4 92/06/17 05:22:02 torek Exp $ 14 */ 15 16 /* 17 * Sun-4 (sort of) and 4c (Campus, i.e., SparcStation) control registers 18 * (includes address space definitions and registers in control space). 19 * 20 * Address space identifiers are 8 bits (0 through 255), but we 21 * only use four of them. 22 */ 23 24 /* 0 unused */ 25 /* 1 unused */ 26 #define ASI_CONTROL 2 /* cache enable, context reg, etc */ 27 #define ASI_SEGMAP 3 /* segment maps (so we can reach each pmeg) */ 28 #define ASI_PTE 4 /* PTE space (pmegs) */ 29 /* 5 unused */ 30 /* 6 unused */ 31 /* 7 unused */ 32 #define ASI_USERI 8 /* I-space (user) */ 33 #define ASI_KERNELI 9 /* I-space (kernel) */ 34 #define ASI_USERD 10 /* D-space (user) */ 35 #define ASI_KERNELD 11 /* D-space (kernel) */ 36 #define ASI_FLUSHSEG 12 /* causes hardware to flush cache segment */ 37 #define ASI_FLUSHPG 13 /* causes hardware to flush cache page */ 38 #define ASI_FLUSHCTX 14 /* causes hardware to flush cache context */ 39 #ifdef SUN4 40 #define ASI_DCACHE 15 /* flush data cache; not used on 4c */ 41 #endif 42 /* 16 through 255 unused (and probably wrap, but who cares?) */ 43 44 /* registers in the control space */ 45 #define AC_CONTEXT 0x30000000 /* context register (byte) */ 46 #define AC_SYSENABLE 0x40000000 /* system enable register (byte) */ 47 #define AC_CACHETAGS 0x80000000 /* cache tag base address */ 48 #define AC_SERIAL 0xf0000000 /* special serial port sneakiness */ 49 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 50 51 #ifdef SUN4 52 #define AC_DVMA_ENABLE 0x50000000 /* enable user dvma */ 53 #define AC_BUS_ERR 0x60000000 /* bus error register */ 54 #define AC_DIAG_REG 0x70000000 /* diagnostic reg */ 55 #define AC_DVMA_MAP 0xd0000000 /* user dvma map entries */ 56 #endif 57 58 #ifdef SUN4C 59 #define AC_SYNC_ERR 0x60000000 /* sync (memory) error reg */ 60 #define AC_SYNC_VA 0x60000004 /* sync error virtual addr */ 61 #define AC_ASYNC_ERR 0x60000008 /* async error reg */ 62 #define AC_ASYNC_VA 0x6000000c /* async error virtual addr */ 63 #define AC_CACHEDATA 0x90000000 /* cached data */ 64 65 /* 66 * Bits in sync error register. Reading the register clears these; 67 * otherwise they accumulate. The error(s) occurred at the virtual 68 * address stored in the sync error address register, and may have 69 * been due to, e.g., what would usually be called a page fault. 70 * Worse, the bits accumulate during instruction prefetch, so 71 * various bits can be on that should be off. 72 */ 73 #define SER_WRITE 0x8000 /* error occurred during write */ 74 #define SER_INVAL 0x80 /* PTE had PG_V off */ 75 #define SER_PROT 0x40 /* operation violated PTE prot */ 76 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 77 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 78 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 79 #define SER_SZERR 0x02 /* size error, whatever that is */ 80 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 81 82 #define SER_BITS \ 83 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 84 85 /* 86 * Bits in async error register (errors from DVMA or Sun-4 cache 87 * writeback). The corresponding bit is also set in the sync error reg. 88 * 89 * A writeback invalid error means there is a bug in the PTE manager. 90 * 91 * The word is that the async error register does not work right. 92 */ 93 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 94 #define AER_TIMEOUT 0x20 /* bus timeout */ 95 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 96 97 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 98 99 #endif /* SUN4C */ 100 101 /* 102 * Bits in system enable register. 103 */ 104 #define SYSEN_DVMA 0x20 /* enable dvma */ 105 #define SYSEN_CACHE 0x10 /* enable cache */ 106 #define SYSEN_RESET 0x04 /* reset the hardware */ 107