1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)fsr.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: fsr.h,v 1.6 92/11/26 02:04:36 torek Exp $ 19 */ 20 21 #ifndef _MACHINE_FSR_H_ 22 #define _MACHINE_FSR_H_ 23 24 /* 25 * Bits in FSR. 26 */ 27 #define FSR_RD 0xc0000000 /* rounding direction */ 28 #define FSR_RD_RN 0 /* round to nearest */ 29 #define FSR_RD_RZ 1 /* round towards 0 */ 30 #define FSR_RD_RP 2 /* round towards +inf */ 31 #define FSR_RD_RM 3 /* round towards -inf */ 32 #define FSR_RD_SHIFT 30 33 #define FSR_RD_MASK 0x03 34 35 #define FSR_RP 0x30000000 /* extended rounding precision */ 36 #define FSR_RP_X 0 /* extended stays extended */ 37 #define FSR_RP_S 1 /* extended => single */ 38 #define FSR_RP_D 2 /* extended => double */ 39 #define FSR_RP_80 3 /* extended => 80-bit */ 40 #define FSR_RP_SHIFT 28 41 #define FSR_RP_MASK 0x03 42 43 #define FSR_TEM 0x0f800000 /* trap enable mask */ 44 #define FSR_TEM_SHIFT 23 45 #define FSR_TEM_MASK 0x1f 46 47 #define FSR_NS 0x00400000 /* ``nonstandard mode'' */ 48 #define FSR_AU 0x00400000 /* aka abrupt underflow mode */ 49 #define FSR_MBZ 0x00300000 /* reserved; must be zero */ 50 51 #define FSR_VER 0x000e0000 /* version bits */ 52 #define FSR_VER_SHIFT 17 53 #define FSR_VER_MASK 0x07 54 55 #define FSR_FTT 0x0001c000 /* FP trap type */ 56 #define FSR_TT_NONE 0 /* no trap */ 57 #define FSR_TT_IEEE 1 /* IEEE exception */ 58 #define FSR_TT_UNFIN 2 /* unfinished operation */ 59 #define FSR_TT_UNIMP 3 /* unimplemented operation */ 60 #define FSR_TT_SEQ 4 /* sequence error */ 61 #define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */ 62 #define FSR_FTT_SHIFT 14 63 #define FSR_FTT_MASK 0x03 64 65 #define FSR_QNE 0x00002000 /* queue not empty */ 66 #define FSR_PR 0x00001000 /* partial result */ 67 68 #define FSR_FCC 0x00000c00 /* FP condition codes */ 69 #define FSR_CC_EQ 0 /* f1 = f2 */ 70 #define FSR_CC_LT 1 /* f1 < f2 */ 71 #define FSR_CC_GT 2 /* f1 > f2 */ 72 #define FSR_CC_UO 3 /* (f1,f2) unordered */ 73 #define FSR_FCC_SHIFT 10 74 #define FSR_FCC_MASK 0x03 75 76 #define FSR_AX 0x000003e0 /* accrued exceptions */ 77 #define FSR_AX_SHIFT 5 78 #define FSR_AX_MASK 0x1f 79 #define FSR_CX 0x0000001f /* current exceptions */ 80 #define FSR_CX_SHIFT 0 81 #define FSR_CX_MASK 0x1f 82 83 /* The following exceptions apply to TEM, AX, and CX. */ 84 #define FSR_NV 0x10 /* invalid operand */ 85 #define FSR_OF 0x08 /* overflow */ 86 #define FSR_UF 0x04 /* underflow */ 87 #define FSR_DZ 0x02 /* division by zero */ 88 #define FSR_NX 0x01 /* inexact result */ 89 90 #endif /* _MACHINE_FSR_H_ */ 91