1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)bwtworeg.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: bwtworeg.h,v 1.4 92/11/26 02:28:05 torek Exp $ 19 */ 20 21 /* 22 * bwtwo display registers. 23 * 24 * The registers start at offset 0x400000 and repeat every 32 bytes 25 * (presumably only the low order address lines are decoded). Video RAM 26 * starts at offset 0x800000. We use separate pointers to each so that 27 * the sparc addressing modes work well. 28 */ 29 struct bwtworeg { 30 /* 31 * The xxx0 range is all 0xff on my IPC but causes a screen glitch 32 * on my SS1+, so it must do *some*thing... the xxx1 range is full 33 * of values but I do not know what they are. bw_ctl changes for 34 * a blanked screen. 35 */ 36 char bw_xxx0[16]; 37 u_char bw_ctl; /* contains video enable */ 38 char bw_xxx1[15]; 39 }; 40 41 /* bits in bw_ctl */ 42 #define CTL_VE 0x40 /* video enable */ 43 44 /* offsets */ 45 #define BWREG_ID 0 46 #define BWREG_REG 0x400000 47 #define BWREG_MEM 0x800000 48 49 /* same, but for gdb */ 50 struct bwtwo_all { 51 long ba_id; /* ID = 0xfe010104 on my IPC */ 52 char ba_xxx0[0x400000-4]; 53 struct bwtworeg ba_reg; /* control registers */ 54 char ba_xxx1[0x400000-32]; 55 char ba_ram[4096]; /* actually larger */ 56 }; 57