1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)cgthreereg.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: cgthreereg.h,v 1.5 92/11/26 02:28:07 torek Exp $ 19 */ 20 21 /* 22 * cgthree display registers. 23 * 24 * The registers start at offset 0x400000 and repeat every 32 bytes 25 * (presumably only the low order address lines are decoded). Video RAM 26 * starts at offset 0x800000. We use separate pointers to each so that 27 * the sparc addressing modes work well. 28 * 29 * The cg3 has a Brooktree Bt458 (?) chip to do everything (Brooktree 30 * makes the only decent color frame buffer chips). To update the 31 * color map one would normally do byte writes, but the hardware 32 * takes longword writes. Since there are three registers for each 33 * color map entry (R, then G, then B), we have to set color 1 with 34 * a write to address 0 (setting 0's R/G/B and color 1's R) followed 35 * by a second write to address 1 (setting color 1's G/B and color 2's 36 * R/G). Software must therefore keep a copy of the current map. 37 * 38 * The colormap address register increments automatically, so the above 39 * write is done as: 40 * 41 * p->cg3_cadr = 0; 42 * p->cg3_cmap = R0G0B0R1; 43 * p->cg3_cmap = G1B1R2G2; 44 * 45 * Yow! 46 */ 47 struct cgthreereg { 48 u_int cg3_addr; /* ?any? address register */ 49 u_int cg3_cmap; /* colormap data register */ 50 u_int cg3_ctrl; /* control register */ 51 u_int cg3_omap; /* overlay map register */ 52 char cg3_xxx0[16]; /* ? (make same size as bwtwo) */ 53 }; 54 55 /* offsets */ 56 #define CG3REG_ID 0 57 #define CG3REG_REG 0x400000 58 #define CG3REG_MEM 0x800000 59 60 /* same, but for gdb */ 61 struct cgthree_all { 62 long ba_id; /* ID = 0xfe010104 on my IPC */ 63 char ba_xxx0[0x400000-4]; 64 struct cgthreereg ba_reg; /* control registers */ 65 char ba_xxx1[0x400000-32]; 66 char ba_ram[4096]; /* actually larger */ 67 }; 68