1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)dmareg.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: dmareg.h,v 1.6 93/04/27 14:39:17 torek Exp $ (LBL) 19 */ 20 21 /* 22 * Sun-4c Sbus slot 0 DMA registers. 23 * 24 * Note that the dma_addr on the rev 1 gate array cannot increment 25 * across a 16 MB boundary (the counter is only 24 bits wide; the 26 * top 8 bits are simply latched). 27 */ 28 struct dmareg { 29 u_long dma_csr; /* control/status register */ 30 u_long dma_addr; /* address (virtual: is fed to MMU) */ 31 u_long dma_bc; /* byte count (not used) */ 32 u_long dma_diag; /* diagnostic register (not used) */ 33 }; 34 35 /* 36 * Bits in dma_csr. 37 * DMA chip revision numbers are confusing (rev 3 = `DMA2'?!). 38 * Not my fault; we just live with what they give us.... 39 * 40 * Notes in [brackets]: 41 * 1: used this way in rev 1 (`DMA') chips. 42 * 2: used this way in rev 2 (`DMA+') chips. 43 * 3: used this way in rev 3 (`DMA2') chips. 44 * R: not self-clearing, must be reset after being set. 45 * D: `drain' is like Unibus `bdp purge', i.e., it tells 46 * the chip to finish up, because there is no more data 47 * going into the buffer register. Supposed to be needed 48 * only in rev 1, but apparently needed or harmless in all 49 * revs. Self-clearing (hence write-only). 50 * I: also enables scsi interrupts. 51 */ 52 #define DMA_REV(csr) (((csr) >> 28) & 0xf) /* device id field */ 53 #define DMAREV_1 0x8 /* rev 1 DMA gate array */ 54 #define DMAREV_2 0x9 /* rev 2 DMA gate array (`DMA+') */ 55 #define DMAREV_3 0xa /* rev 3 DMA gate array (`DMA2') */ 56 57 #define DMA_1ZERO 0x0fff0000 /* unused; reads as zero [1] */ 58 #define DMA_NAL 0x08000000 /* next address loaded [2] (ro) */ 59 #define DMA_AL 0x04000000 /* address loaded [2] (ro) */ 60 #define DMA_ON 0x02000000 /* working [2] (ro) */ 61 #define DMA_NAE 0x01000000 /* next-address enable [2] (rw) */ 62 #define DMA_DTCI 0x00800000 /* disable DMA_TC intr [2] (rw) */ 63 #define DMA_TURBO 0x00400000 /* faster 53C90A mode [2] (rw) */ 64 #define DMA_LERR 0x00200000 /* LANCE error [2] (ro) */ 65 #define DMA_TWOCYCLE 0x00200000 /* two cycle mode [3] (rw?) */ 66 #define DMA_ALE 0x00100000 /* LANCE addr latch ena [2] (rw) */ 67 #define DMA_2ZERO 0x000f0000 /* unused; reads as zero [2] */ 68 #define DMA_BURSTMASK 0x000c0000 /* burst mode mask [3] */ 69 #define DMA_BURST16 0x00000000 /* 16-byte bursts (default) */ 70 #define DMA_BURST32 0x00040000 /* 32-byte bursts */ 71 #define DMA_BURST0 0x00080000 /* no bursts */ 72 #define DMA_ILACC 0x00008000 /* for new AMD ethernet chip [1,2] */ 73 #define DMA_TC 0x00004000 /* terminal cnt: dma_bc ran out [1,2] */ 74 #define DMA_BCE 0x00002000 /* byte count enable (leave 0) */ 75 #define DMA_BO 0x00001800 /* byte offset [1] (ro) */ 76 #define DMA_RP 0x00000400 /* busy, plz don't flush [1] (ro) */ 77 #define DMA_ENA 0x00000200 /* enable the dma chip */ 78 #define DMA_READ 0x00000100 /* set for dev=>mem, i.e., read() */ 79 #define DMA_RESET 0x00000080 /* reset dma chip [R] */ 80 #define DMA_DRAIN 0x00000040 /* drain buffered data [D,1] (wo) */ 81 #define DMA_SLAVEERR 0x00000040 /* slave error [2,3] (ro) */ 82 #define DMA_FLUSH 0x00000020 /* clear PC, EP, and TC [2,3] (wo) */ 83 #define DMA_IE 0x00000010 /* interrupt enable [2,3,I] */ 84 #define DMA_PC 0x0000000c /* bytes in pack reg [1] (ro) */ 85 #define DMA_DRAINING 0x0000000c /* nonzero => draining [2,3] (ro) */ 86 #define DMA_EP 0x00000002 /* error pending (ro) */ 87 #define DMA_IP 0x00000001 /* interrupt pending (ro) */ 88 89 #define DMA_REV1_BITS \ 90 "\20\20ILACC\17TC\16BCE\13RP\12ENA\11READ\10RESET\7DRAIN\2EP\1IP" 91 92 /* Look ma, second system syndrome! */ 93 #define DMA_REV2_BITS \ 94 "\20\34NAL\33AL\32ON\31NAE\30DTCI\27TURBO\26LERR\25ALE\ 95 \20ILACC\17TC\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP" 96 97 /* (Note how most of the crap has been discarded now.) */ 98 #define DMA_REV3_BITS \ 99 "\20\26TWOCYCLE\16BCE\12ENA\11READ\10RESET\7SLAVEERR\6FLUSH\5IE\2EP\1IP" 100 101 /* DMA_BYTE turns the DMA_BO field into a byte index */ 102 #define DMA_BYTE(csr) (((csr) >> 11) & 3) 103 104 /* DMA_NPACK turns the DMA_PC field into a byte count */ 105 #define DMA_NPACK(csr) (((csr) >> 2) & 3) 106 107 /* DMA_INTR is true if the DMA chip says an ESP or DMA interrupt is pending */ 108 #define DMA_INTR(csr) ((csr) & (DMA_IP | DMA_EP)) 109