1 /* 2 * Copyright (c) 1988, 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)esp.c 8.3 (Berkeley) 05/03/94 17 * 18 * from: $Header: esp.c,v 1.28 93/04/27 14:40:44 torek Exp $ (LBL) 19 * 20 * Loosely derived from Mary Baker's devSCSIC90.c from the Berkeley 21 * Sprite project, which is: 22 * 23 * Copyright 1988 Regents of the University of California 24 * Permission to use, copy, modify, and distribute this 25 * software and its documentation for any purpose and without 26 * fee is hereby granted, provided that the above copyright 27 * notice appear in all copies. The University of California 28 * makes no representations about the suitability of this 29 * software for any purpose. It is provided "as is" without 30 * express or implied warranty. 31 * 32 * from /sprite/src/kernel/dev/sun4c.md/RCS/devSCSIC90.c,v 1.4 33 * 90/12/19 12:37:58 mgbaker Exp $ SPRITE (Berkeley) 34 */ 35 36 /* 37 * Sbus ESP/DMA driver. A single driver must be used for both devices 38 * as they are physically tied to each other: The DMA chip can only 39 * be used to assist ESP SCSI transactions; the ESP interrupt enable is 40 * in the DMA chip csr. 41 * 42 * Since DMA and SCSI interrupts are handled in the same routine, the 43 * DMA device does not declare itself as an sbus device. This saves 44 * some space. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/buf.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 52 #include <dev/scsi/scsi.h> 53 #include <dev/scsi/scsivar.h> 54 55 #include <machine/autoconf.h> 56 #include <machine/cpu.h> 57 58 #include <sparc/sbus/dmareg.h> 59 #define ESP_PHASE_NAMES 60 #include <sparc/sbus/espreg.h> 61 #include <sparc/sbus/sbusvar.h> 62 63 #include <libkern/libkern.h> 64 65 /* 66 * This driver is largely a giant state machine: 67 * 68 * Given some previous SCSI state (as set up or tracked by us 69 * earlier) and the interrupt registers provided on the chips 70 * (dmacsr, espstat, espstep, and espintr), derive an action. 71 * In many cases this is just a matter of reading the target's 72 * phase and following its orders, which sets a new state. 73 * 74 * This sequencing is done in espact(); the state is primed in espselect(). 75 * 76 * Data transfer is always done via DMA. Unfortunately, there are 77 * limits in the DMA and ESP chips on how much data can be moved 78 * in a single operation. The ESP chip has a 16-bit counter, so 79 * it is limited to 65536 bytes. More insidiously, while the DMA 80 * chip has a 32-bit address, this is composed of a 24-bit counter 81 * with an 8-bit latch, so it cannot cross a 16 MB boundary. To 82 * handle these, we program a smaller count than our caller requests; 83 * when this shorter transfer is done, if the target is still up 84 * for data transfer, we simply keep going (updating the DMA address) 85 * as needed. 86 * 87 * Another state bit is used to recover from bus resets: 88 * 89 * A single TEST UNIT READY is attempted on each target before any 90 * real communication begins; this TEST UNIT READY is allowed to 91 * fail in any way. This is required for the Quantum ProDrive 100 92 * MB disks, for instance, which respond to their first selection 93 * with status phase, and for anything that insists on implementing 94 * the broken SCSI-2 synch transfer initial message. 95 * 96 * This is done in espclear() (which calls espselect(); functions that 97 * call espselect() must check for clearing first). 98 * 99 * The state machines actually intermingle, as some SCSI sequences are 100 * only allowed during clearing. 101 */ 102 103 /* per-DMA variables */ 104 struct dma_softc { 105 struct device dc_dev; /* base device */ 106 volatile struct dmareg *dc_dma; /* register virtual address */ 107 int dc_dmarev; /* revision */ 108 char *dc_dmafmt; /* format for error messages */ 109 }; 110 void dmaattach(struct device *, struct device *, void *); 111 struct cfdriver dmacd = 112 { NULL, "dma", matchbyname, dmaattach, DV_DULL, sizeof(struct dma_softc) }; 113 114 /* per-ESP variables */ 115 struct esp_softc { 116 /* 117 * External interfaces. 118 */ 119 struct hba_softc sc_hba; /* base device + hba, must be first */ 120 #define sc_dev sc_hba.hba_dev 121 struct sbusdev sc_sd; /* sbus device */ 122 struct intrhand sc_ih; /* interrupt entry */ 123 struct evcnt sc_intrcnt; /* interrupt counter */ 124 struct dma_softc *sc_dc; /* pointer to corresponding dma sc */ 125 126 /* 127 * Addresses mapped to hardware registers. 128 */ 129 volatile struct espreg *sc_esp; 130 volatile struct dmareg *sc_dma; 131 132 /* 133 * Copies of registers cleared/unlatched by reading. 134 * (FIFO flags is not cleared, but we want it for debugging.) 135 */ 136 u_long sc_dmacsr; 137 u_char sc_espstat; 138 u_char sc_espstep; 139 u_char sc_espintr; 140 u_char sc_espfflags; 141 142 /* miscellaneous */ 143 int sc_clockfreq; /* clock frequency */ 144 u_char sc_sel_timeout; /* select timeout */ 145 u_char sc_id; /* initiator ID (default = 7) */ 146 u_char sc_needclear; /* uncleared targets (1 bit each) */ 147 u_char sc_esptype; /* 100, 100A, 2xx (see below) */ 148 u_char sc_ccf; /* clock conversion factor */ 149 u_char sc_conf1; /* value for config reg 1 */ 150 u_char sc_conf2; /* value for config reg 2 */ 151 u_char sc_conf3; /* value for config reg 3 */ 152 struct bootpath *sc_bp; /* esp bootpath so far */ 153 154 /* 155 * Information pertaining to the current transfer, 156 * including sequencing. 157 * 158 * The size of sc_msg is the size of the ESP fifo, 159 * since we do message-in simply by allowing the fifo to fill. 160 */ 161 char sc_probing; /* used during autoconf; see below */ 162 char sc_clearing; /* true => cmd is just to clear targ */ 163 char sc_iwant; /* true => icmd needs wakeup on idle */ 164 char sc_state; /* SCSI protocol state; see below */ 165 char sc_sentcmd; /* set once we get cmd out */ 166 char sc_dmaactive; /* true => doing dma */ 167 #ifdef notyet 168 u_char sc_sync; /* synchronous transfer stuff (?) */ 169 #endif 170 u_char sc_stat[2]; /* status from last `status' phase */ 171 u_char sc_msg[16]; /* message from device */ 172 u_short sc_dmactl; /* control to load into dma csr */ 173 u_long sc_dmaaddr; /* address for next xfer */ 174 int sc_dmasize; /* size of current xfer */ 175 int sc_resid; /* count of bytes not yet xferred */ 176 int sc_targ; /* the target involved */ 177 struct scsi_cdb *sc_curcdb; /* ptr to current command */ 178 /* might cdbspace eventually be per-target? */ 179 struct scsi_cdb sc_cdbspace; /* space for one command */ 180 }; 181 182 /* 183 * Values for sc_esptype (used to control configuration reset, and for 184 * workarounds for chip bugs). The order is important; see espreset(). 185 */ 186 #define ESP100 0 187 #define ESP100A 1 188 #define ESP2XX 2 189 190 /* 191 * Probe state. 0 means not probing. While looking for each target 192 * we set this to PROBE_TESTING and do a TEST UNIT READY on unit 0. 193 * If selection fails, this is changed to PROBE_NO_TARGET; otherwise 194 * we assume the target exists, regardless of the result of the test. 195 */ 196 #define PROBE_TESTING 1 197 #define PROBE_NO_TARGET 2 198 199 /* 200 * States in sc_state. 201 * 202 * Note that S_SVC is rare: normally we load the SCSI command into the 203 * ESP fifo and get interrupted only when the device has gone to data 204 * or status phase. If the device wants to play games, though, we end 205 * up doing things differently. 206 */ 207 char *espstates[] = { 208 #define S_IDLE 0 /* not doing anything */ 209 "idle", 210 #define S_SEL 1 /* expecting select done interrupt */ 211 "selecting", 212 #define S_SVC 2 /* expecting service req interrupt */ 213 "waiting for svc req", 214 #define S_DI 3 /* expecting data-in done interrupt */ 215 "receiving data", 216 #define S_DO 4 /* expecting data-out done interrupt */ 217 "sending data", 218 #define S_STAT 5 /* expecting status done interrupt */ 219 "receiving status", 220 #define S_MI 6 /* expecting message-in done interrupt */ 221 "receiving message", 222 #define S_FI 7 /* expecting final disconnect interrupt */ 223 "waiting for disconnect" 224 }; 225 226 /* 227 * Hardware limits on transfer sizes (see comments at top). 228 */ 229 #define ESPMAX (64 * 1024) 230 #define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff)) 231 232 /* 233 * Return values from espact(). 234 */ 235 #define ACT_CONT 0 /* espact() handled everything */ 236 #define ACT_IO 1 /* espact() is xferring data */ 237 #define ACT_DONE 2 /* handled everything, and op is now done */ 238 #define ACT_ERROR 3 /* an error occurred, op has been trashed */ 239 #define ACT_RESET 4 /* please reset ESP, then do ACT_ERROR */ 240 #define ACT_QUICKINTR 5 /* another interrupt is expected immediately */ 241 242 /* autoconfiguration driver */ 243 void espattach(struct device *, struct device *, void *); 244 struct cfdriver espcd = 245 { NULL, "esp", matchbyname, espattach, DV_DULL, sizeof(struct esp_softc), 246 "intr" }; 247 248 /* Sbus driver */ 249 void espsbreset(struct device *); 250 251 /* interrupt interface */ 252 int espintr(void *); 253 254 /* SCSI HBA driver */ 255 int espicmd(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int, int); 256 int espdump(struct hba_softc *, int, struct scsi_cdb *, caddr_t, int); 257 void espstart(struct device *, struct sq *, struct buf *, 258 scdgo_fn, struct device *); 259 int espgo(struct device *, int, scintr_fn, struct device *, 260 struct buf *, int); 261 void esprel(struct device *); 262 void esphbareset(struct hba_softc *, int); 263 static struct hbadriver esphbadriver = 264 { espicmd, espdump, espstart, espgo, esprel, esphbareset }; 265 266 /* other prototypes */ 267 static void espdoattach(int); 268 static void dmareset(struct esp_softc *); 269 static void espreset(struct esp_softc *, int); 270 static void esperror(struct esp_softc *, const char *); 271 static int espact(struct esp_softc *); 272 void espselect(struct esp_softc *, int, struct scsi_cdb *); 273 274 /* second arg to espreset() */ 275 #define RESET_ESPCHIP 0x1 276 #define RESET_SCSIBUS 0x2 277 #define RESET_BOTH (RESET_ESPCHIP | RESET_SCSIBUS) 278 279 /* 280 * Attach a found DMA chip. 281 * The second argument is really a pointer to an sbus_attach_args. 282 */ 283 void 284 dmaattach(parent, dev, args) 285 struct device *parent; 286 struct device *dev; 287 void *args; 288 { 289 register struct dma_softc *dc = (struct dma_softc *)dev; 290 register struct sbus_attach_args *sa = args; 291 register volatile struct dmareg *dma; 292 register int rev; 293 struct esp_softc *esc; 294 295 if (sa->sa_ra.ra_vaddr) 296 dma = (volatile struct dmareg *)sa->sa_ra.ra_vaddr; 297 else 298 dma = (volatile struct dmareg *) 299 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct dmareg)); 300 dc->dc_dma = dma; 301 302 switch (rev = DMA_REV(dma->dma_csr)) { 303 case DMAREV_1: 304 printf(": rev 1\n"); 305 dc->dc_dmafmt = DMA_REV1_BITS; 306 break; 307 case DMAREV_2: 308 printf(": rev 2\n"); 309 dc->dc_dmafmt = DMA_REV2_BITS; 310 break; 311 case DMAREV_3: 312 printf(": rev 3\n"); 313 printf("WARNING: esp.c not yet updated for rev 3\n"); 314 dc->dc_dmafmt = DMA_REV3_BITS; 315 break; 316 default: 317 printf(": unknown revision code 0x%x\n", rev); 318 dc->dc_dmafmt = DMA_REV3_BITS; /* cross fingers */ 319 break; 320 } 321 dc->dc_dmarev = rev; 322 espdoattach(dc->dc_dev.dv_unit); 323 } 324 325 /* 326 * Attach a found ESP chip. Search for targets; attach each one found. 327 * The latter must be deferred if the corresponding dma chip has not yet 328 * been configured. 329 */ 330 void 331 espattach(parent, self, args) 332 struct device *parent; 333 struct device *self; 334 void *args; 335 { 336 register struct esp_softc *sc = (struct esp_softc *)self; 337 register struct sbus_attach_args *sa = args; 338 register volatile struct espreg *esp; 339 register struct bootpath *bp; 340 int node, pri, freq, t; 341 342 if (sa->sa_ra.ra_nintr != 1) { 343 printf(": expected 1 interrupt, got %d\n", sa->sa_ra.ra_nintr); 344 return; 345 } 346 pri = sa->sa_ra.ra_intr[0].int_pri; 347 printf(" pri %d", pri); 348 if (sa->sa_ra.ra_vaddr) 349 esp = (volatile struct espreg *)sa->sa_ra.ra_vaddr; 350 else 351 esp = (volatile struct espreg *) 352 mapiodev(sa->sa_ra.ra_paddr, sizeof(struct espreg)); 353 sc->sc_esp = esp; 354 node = sa->sa_ra.ra_node; 355 sc->sc_id = getpropint(node, "initiator-id", 7); 356 freq = getpropint(node, "clock-frequency", -1); 357 if (freq < 0) 358 freq = 359 ((struct sbus_softc *)sc->sc_dev.dv_parent)->sc_clockfreq; 360 361 /* MIGHT NEED TO RESET ESP CHIP HERE ...? */ 362 363 /* 364 * Find out whether we have a -100, -100A, or -2xx, 365 * and what speed it runs at. 366 */ 367 sc->sc_conf1 = sc->sc_id | ESPCONF1_PARENB; 368 /* sc->sc_conf2 = 0; */ 369 /* sc->sc_conf3 = 0; */ 370 esp->esp_conf1 = sc->sc_conf1; 371 esp->esp_conf2 = 0; 372 esp->esp_conf2 = ESPCONF2_SCSI2 | ESPCONF2_RPE; 373 if ((esp->esp_conf2 & ~ESPCONF2_RSVD) != 374 (ESPCONF2_SCSI2 | ESPCONF2_RPE)) { 375 printf(": ESP100"); 376 sc->sc_esptype = ESP100; 377 } else { 378 esp->esp_conf2 = 0; 379 esp->esp_conf3 = 0; 380 esp->esp_conf3 = 5; 381 if (esp->esp_conf3 != 5) { /* XXX def bits */ 382 printf(": ESP100A"); 383 sc->sc_esptype = ESP100A; 384 } else { 385 esp->esp_conf3 = 0; 386 printf(": ESP2XX"); 387 sc->sc_esptype = ESP2XX; 388 } 389 } 390 printf(", clock = %s MHz, ID = %d\n", clockfreq(freq), sc->sc_id); 391 392 /* 393 * Set clock conversion factor and select timeout. 394 * N.B.: clock frequency is not actually used in the rest 395 * of the driver; I calculate it here for completeness only 396 * (so I can see it when debugging). 397 */ 398 sc->sc_clockfreq = freq; 399 freq = howmany(freq, 1000 * 1000); /* convert to MHz */ 400 t = ESPCCF_FROMMHZ(freq); 401 if (t < ESPCCF_MIN) 402 t = ESPCCF_MIN; 403 sc->sc_ccf = t; 404 t = ESPTIMO_REGVAL(250, t, freq); /* timeout = 250 ms. */ 405 if (t >= 256) 406 t = 0; 407 sc->sc_sel_timeout = t; 408 409 /* 410 * Link into sbus; set interrupt handler. 411 */ 412 sc->sc_sd.sd_reset = espsbreset; 413 sbus_establish(&sc->sc_sd, &sc->sc_dev); 414 sc->sc_ih.ih_fun = espintr; 415 sc->sc_ih.ih_arg = sc; 416 intr_establish(pri, &sc->sc_ih); 417 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 418 419 #define SAME_ESP(bp, sa) \ 420 ((bp->val[0] == sa->sa_slot && bp->val[1] == sa->sa_offset) || \ 421 (bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit)) 422 423 bp = sa->sa_ra.ra_bp; 424 if (bp != NULL && strcmp(bp->name, "esp") == 0 && SAME_ESP(bp, sa)) 425 sc->sc_bp = bp + 1; 426 espdoattach(sc->sc_dev.dv_unit); 427 } 428 429 /* 430 * `Final' attach of esp occurs once esp and dma chips have been found 431 * and assigned virtual addresses. Set up the ESP SCSI data structures 432 * and probe the SCSI bus. 433 */ 434 static void 435 espdoattach(unit) 436 int unit; 437 { 438 register struct esp_softc *sc; 439 register struct dma_softc *dc; 440 register struct bootpath *bp; 441 register struct targ *t; 442 register int targ, u; 443 444 /* make sure we have both */ 445 if (espcd.cd_ndevs <= unit || 446 dmacd.cd_ndevs <= unit || 447 (sc = espcd.cd_devs[unit]) == NULL || 448 (dc = dmacd.cd_devs[unit]) == NULL) 449 return; 450 sc->sc_dc = dc; 451 sc->sc_dma = dc->dc_dma; 452 sc->sc_hba.hba_driver = &esphbadriver; 453 454 sc->sc_dma->dma_csr = 0; /* ??? */ 455 espreset(sc, RESET_ESPCHIP); 456 457 /* MAYBE THIS SHOULD BE MOVED TO scsi_subr.c? */ 458 for (targ = 0; targ < 8; targ++) { 459 if (targ == sc->sc_id) 460 continue; 461 sc->sc_probing = PROBE_TESTING; 462 sc->sc_clearing = 1; 463 (void)scsi_test_unit_ready(&sc->sc_hba, targ, 0); 464 if (sc->sc_probing != PROBE_NO_TARGET) { 465 sc->sc_probing = 0; 466 sc->sc_clearing = 0; 467 SCSI_FOUNDTARGET(&sc->sc_hba, targ); 468 } 469 } 470 sc->sc_probing = 0; 471 sc->sc_clearing = 0; 472 473 /* 474 * See if we booted from a unit on this target. We could 475 * compare bp->name against the unit's name but there's no 476 * real need since a target and unit uniquely specify a 477 * scsi device. 478 */ 479 if ((bp = sc->sc_bp) != NULL && (u_int)(targ = bp->val[0]) < 8 && 480 (u_int)(u = bp->val[1]) < 8 && 481 (t = sc->sc_hba.hba_targets[targ]) != NULL && t->t_units[u] != NULL) 482 bootdv = t->t_units[u]->u_dev; 483 } 484 485 /* 486 * We are not allowed to touch the DMA "flush" and "drain" bits 487 * while it is still thinking about a request (DMA_RP). 488 */ 489 #define DMAWAIT(dma) while ((dma)->dma_csr & DMA_RP) DELAY(1) 490 #define DMAWAIT1(dma) while ((dma)->dma_csr & DMA_PC) DELAY(1) 491 492 /* 493 * Reset the DMA chip. 494 */ 495 static void 496 dmareset(sc) 497 struct esp_softc *sc; 498 { 499 register volatile struct dmareg *dma = sc->sc_dma; 500 501 DMAWAIT(dma); 502 dma->dma_csr |= DMA_RESET; 503 DELAY(200); 504 dma->dma_csr &= ~DMA_RESET; /* ??? */ 505 sc->sc_dmaactive = 0; 506 if (sc->sc_dc->dc_dmarev == DMAREV_2 && sc->sc_esptype != ESP100) 507 dma->dma_csr |= DMA_TURBO; 508 dma->dma_csr |= DMA_IE; /* enable interrupts */ 509 DELAY(200); 510 } 511 512 /* 513 * Reset the chip and/or SCSI bus (always resets DMA). 514 */ 515 static void 516 espreset(sc, how) 517 register struct esp_softc *sc; 518 int how; 519 { 520 register volatile struct espreg *esp = sc->sc_esp; 521 522 dmareset(sc); 523 if (how & RESET_ESPCHIP) { 524 esp->esp_cmd = ESPCMD_RESET_CHIP; 525 esp->esp_cmd = ESPCMD_NOP; 526 /* 527 * Reload configuration registers (cleared by 528 * RESET_CHIP command). Reloading conf2 on an 529 * ESP100 goofs it up, so out of paranoia we load 530 * only the registers that exist. 531 */ 532 esp->esp_conf1 = sc->sc_conf1; 533 if (sc->sc_esptype > ESP100) { /* 100A, 2XX */ 534 esp->esp_conf2 = sc->sc_conf2; 535 if (sc->sc_esptype > ESP100A) /* 2XX only */ 536 esp->esp_conf3 = sc->sc_conf3; 537 } 538 esp->esp_ccf = sc->sc_ccf; 539 esp->esp_timeout = sc->sc_sel_timeout; 540 /* We set synch offset later. */ 541 } 542 if (how & RESET_SCSIBUS) { 543 /* 544 * The chip should retain most of its parameters 545 * (including esp_ccf) across this kind of reset 546 * (see section 3.5 of Emulex documentation). 547 */ 548 /* turn off scsi bus reset interrupts and reset scsi bus */ 549 esp->esp_conf1 = sc->sc_conf1 | ESPCONF1_REPORT; 550 esp->esp_cmd = ESPCMD_RESET_BUS; 551 esp->esp_cmd = ESPCMD_NOP; 552 DELAY(100000); /* ??? */ 553 (void)esp->esp_intr; 554 esp->esp_conf1 = sc->sc_conf1; 555 } 556 sc->sc_state = S_IDLE; 557 if (sc->sc_iwant) { 558 wakeup((caddr_t)&sc->sc_iwant); 559 sc->sc_iwant = 0; 560 } 561 sc->sc_needclear = 0xff; 562 } 563 564 /* 565 * Reset the SCSI bus and, optionally, all attached targets. 566 */ 567 void 568 esphbareset(hba, resetunits) 569 struct hba_softc *hba; 570 int resetunits; 571 { 572 register struct esp_softc *sc = (struct esp_softc *)hba; 573 574 espreset(sc, RESET_SCSIBUS); 575 if (resetunits) 576 scsi_reset_units(&sc->sc_hba); 577 } 578 579 /* 580 * Reset the esp, after an Sbus reset. 581 * Also resets corresponding dma chip. 582 * 583 * THIS ROUTINE MIGHT GO AWAY 584 */ 585 void 586 espsbreset(dev) 587 struct device *dev; 588 { 589 struct esp_softc *sc = (struct esp_softc *)dev; 590 591 if (sc->sc_dc) { 592 printf(" %s %s", sc->sc_dc->dc_dev.dv_xname, 593 sc->sc_dev.dv_xname); 594 esphbareset(&sc->sc_hba, 1); 595 } 596 } 597 598 /* 599 * Log an error. 600 */ 601 static void 602 esperror(sc, err) 603 register struct esp_softc *sc; 604 const char *err; 605 { 606 int stat; 607 608 stat = sc->sc_espstat; 609 printf( 610 "%s target %d cmd 0x%x (%s): %s:\n\ 611 \tstat=%b (%s) step=%x dmacsr=%b fflags=%x intr=%b\n", 612 sc->sc_dev.dv_xname, sc->sc_targ, sc->sc_curcdb->cdb_bytes[0], 613 espstates[sc->sc_state], err, 614 stat, ESPSTAT_BITS, espphases[stat & ESPSTAT_PHASE], 615 sc->sc_espstep, sc->sc_dmacsr, sc->sc_dc->dc_dmafmt, 616 sc->sc_espfflags, sc->sc_espintr, ESPINTR_BITS); 617 } 618 619 /* 620 * Issue a select, loading command into the FIFO. 621 * Return nonzero on error, 0 if OK. 622 * Sets state to `selecting'; espact() will sequence state FSM. 623 */ 624 void 625 espselect(sc, targ, cdb) 626 register struct esp_softc *sc; 627 register int targ; 628 register struct scsi_cdb *cdb; 629 { 630 register volatile struct espreg *esp; 631 register int i, cmdlen; 632 633 sc->sc_targ = targ; 634 sc->sc_state = S_SEL; 635 sc->sc_curcdb = cdb; 636 sc->sc_sentcmd = 0; 637 sc->sc_stat[0] = 0xff; /* ??? */ 638 sc->sc_msg[0] = 0xff; /* ??? */ 639 640 /* 641 * Try to talk to target. 642 * Synch offset 0 => asynchronous transfer. 643 */ 644 esp = sc->sc_esp; 645 esp->esp_id = targ; 646 esp->esp_syncoff = 0; 647 648 /* 649 * Stuff the command bytes into the fifo. 650 * Select without attention since we do not do disconnect yet. 651 */ 652 cmdlen = SCSICMDLEN(cdb->cdb_bytes[0]); 653 for (i = 0; i < cmdlen; i++) 654 esp->esp_fifo = cdb->cdb_bytes[i]; 655 esp->esp_cmd = ESPCMD_SEL_NATN; 656 /* the rest is done elsewhere */ 657 } 658 659 /* 660 * Sequence through the SCSI state machine. Return the action to take. 661 * 662 * Most of the work happens here. 663 * 664 * There are three interrupt sources: 665 * -- ESP interrupt request (typically, some device wants something). 666 * -- DMA memory error. 667 * -- DMA byte count has reached 0 (we do not often want this one but 668 * can only turn it off in rev 2 DMA chips, it seems). 669 * DOES THIS OCCUR AT ALL HERE? THERE IS NOTHING TO HANDLE IT! 670 */ 671 static int 672 espact(sc) 673 register struct esp_softc *sc; 674 { 675 register volatile struct espreg *esp; 676 register volatile struct dmareg *dma; 677 register int reg, i, resid, newstate; 678 register struct scsi_cdb *cdb; 679 680 dma = sc->sc_dma; 681 /* check various error conditions, using as little code as possible */ 682 if (sc->sc_dmacsr & DMA_EP) { 683 esperror(sc, "DMA error"); 684 DMAWAIT(dma); 685 dma->dma_csr |= DMA_FLUSH; 686 DMAWAIT1(dma); 687 return (ACT_ERROR); 688 } 689 reg = sc->sc_espstat; 690 if (reg & ESPSTAT_GE) { 691 /* 692 * This often occurs when there is no target. 693 * (See DSC code below.) 694 */ 695 if (sc->sc_espintr & ESPINTR_DSC && 696 sc->sc_state == S_SEL && sc->sc_probing) { 697 sc->sc_probing = PROBE_NO_TARGET; 698 return (ACT_RESET); 699 } 700 esperror(sc, "DIAG: gross error (ignored)"); 701 } 702 if (reg & ESPSTAT_PE) { 703 esperror(sc, "parity error"); 704 return (ACT_RESET); 705 } 706 reg = sc->sc_espintr; 707 #define ERR (ESPINTR_SBR|ESPINTR_ILC|ESPINTR_RSL|ESPINTR_SAT|ESPINTR_SEL) 708 if (reg & ERR) { 709 if (reg & ESPINTR_SBR) 710 esperror(sc, "scsi bus reset"); 711 else if (reg & ESPINTR_ILC) 712 esperror(sc, "illegal command (driver bug)"); 713 else { 714 printf("%s: target %d", sc->sc_dev.dv_xname, 715 sc->sc_targ); 716 if (reg & ESPINTR_RSL) 717 printf(" tried to reselect;"); 718 if (reg & ESPINTR_SAT) 719 printf(" selected with ATN;"); 720 if (reg & ESPINTR_SEL) 721 printf(" selected us as target;"); 722 printf("we do not allow this yet\n"); 723 } 724 return (ACT_ERROR); 725 } 726 #undef ERR 727 728 esp = sc->sc_esp; 729 730 /* 731 * Disconnect currently only allowed in `final interrupt' states. 732 */ 733 if (reg & ESPINTR_DSC) { 734 if (sc->sc_state == S_FI) 735 return (ACT_DONE); 736 /* 737 * If we were doing a select just to test the existence 738 * of the target, note that it did not respond; otherwise 739 * gripe. 740 */ 741 if (sc->sc_state == S_SEL) { 742 if (sc->sc_probing) { 743 sc->sc_probing = PROBE_NO_TARGET; 744 return (ACT_RESET); 745 } 746 } 747 /* flush fifo, in case we were selecting or sending data */ 748 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 749 DELAY(1); 750 printf("%s: target %d not responding\n", 751 sc->sc_dev.dv_xname, sc->sc_targ); 752 return (ACT_ERROR); 753 } 754 755 /* 756 * Okay, things are moving along. 757 * What were we doing the last time we did something, 758 * and did it complete normally? 759 */ 760 switch (sc->sc_state) { 761 762 case S_SEL: 763 /* 764 * We were selecting. Arbitration and select are 765 * complete (because ESPINTR_DSC was not set), but 766 * there is no guarantee the command went out. 767 */ 768 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != 769 (ESPINTR_SVC|ESPINTR_CMP)) { 770 esperror(sc, "selection failed"); 771 return (ACT_RESET); 772 } 773 if (sc->sc_espstep == ESPSTEP_DONE) { 774 sc->sc_sentcmd = 1; 775 break; 776 } 777 if (sc->sc_espstep == 2) { 778 /* 779 * We got something other than command phase. 780 * Just pretend things are normal; the 781 * device will ask for the command later. 782 */ 783 esperror(sc, "DIAG: esp step 2"); 784 } else if (sc->sc_espstep == 3) { 785 /* 786 * Device entered command phase and then exited it 787 * before we finished handing out the command. 788 * Let this happen iff we are trying to clear the 789 * target state. 790 */ 791 esperror(sc, "DIAG: esp step 3"); 792 if (!sc->sc_clearing) 793 return (ACT_RESET); 794 } else { 795 printf("%s: mysterious esp step %d\n", 796 sc->sc_dev.dv_xname, sc->sc_espstep); 797 return (ACT_RESET); 798 } 799 800 /* 801 * Part of the command may still be lodged in the FIFO. 802 */ 803 if (ESP_NFIFO(sc->sc_espfflags)) { 804 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 805 DELAY(1); 806 } 807 break; 808 809 case S_SVC: 810 /* 811 * We were waiting for phase change after stuffing the command 812 * into the FIFO. Make sure it got out. 813 */ 814 if (ESP_NFIFO(sc->sc_espfflags)) { 815 esperror(sc, "DIAG: CMDSVC, fifo not empty"); 816 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 817 DELAY(1); 818 } else 819 sc->sc_sentcmd = 1; 820 break; 821 822 case S_DI: 823 /* 824 * We were doing DMA data in, and expecting a 825 * transfer-count-zero interrupt or a phase change. 826 * We got that; drain the pack register and handle 827 * as for data out -- but ignore FIFO (it should be 828 * empty, except for sync mode which we are not 829 * using anyway). 830 */ 831 DMAWAIT(dma); 832 dma->dma_csr |= DMA_DRAIN; 833 DMAWAIT1(dma); 834 resid = 0; 835 goto dma_data_done; 836 837 case S_DO: 838 /* 839 * We were doing DMA data out. If there is data in the 840 * FIFO, it is stuff that got DMAed out but never made 841 * it to the device, so it counts as residual. 842 */ 843 if ((resid = ESP_NFIFO(sc->sc_espfflags)) != 0) { 844 esp->esp_cmd = ESPCMD_FLUSH_FIFO; 845 DELAY(1); 846 } 847 dma_data_done: 848 if (sc->sc_dmaactive == 0) { 849 esperror(sc, "dma done w/o dmaactive"); 850 panic("espact"); 851 } 852 sc->sc_dmaactive = 0; 853 854 /* Finish computing residual count. */ 855 reg = esp->esp_tcl | (esp->esp_tch << 8); 856 if (reg == 0 && (sc->sc_espstat & ESPSTAT_TC) == 0) 857 reg = 65536; 858 resid += reg; 859 860 /* Compute xfer count (requested - resid). */ 861 i = sc->sc_dmasize - resid; 862 if (i < 0) { 863 printf("%s: xfer resid (%d) > xfer req (%d)\n", 864 sc->sc_dev.dv_xname, resid, sc->sc_dmasize); 865 i = sc->sc_dmasize; /* forgiving... */ 866 } 867 868 /* If data came in we must flush cache. */ 869 if (sc->sc_state == S_DI) 870 cache_flush(sc->sc_dmaaddr, i); 871 sc->sc_dmaaddr += i; 872 sc->sc_resid -= i; 873 if ((sc->sc_espintr & ESPINTR_SVC) == 0) { 874 esperror(sc, "no bus service req"); 875 return (ACT_RESET); 876 } 877 break; 878 879 case S_STAT: 880 /* 881 * The last thing we did was tell it `initiator complete' 882 * and so we expect to have gotten both the status byte 883 * and the final message byte. It is possible that we 884 * got something else.... 885 * 886 * Apparently, BUS SERVICE is set if we got just status, 887 * while FUNCTION COMPLETE is set if we got both. 888 */ 889 if ((reg & (ESPINTR_SVC|ESPINTR_CMP)) != ESPINTR_CMP) { 890 esperror(sc, "bad status interrupt state"); 891 return (ACT_RESET); 892 } 893 reg = ESP_NFIFO(sc->sc_espfflags); 894 if (reg < 2) { 895 printf( 896 "%s: command done but fifo count = %d; must be >= 2\n", 897 sc->sc_dev.dv_xname, reg); 898 return (ACT_RESET); 899 } 900 /* 901 * Read the status and the first msg byte. 902 * It should be CMD_COMPLETE. Eventually we 903 * may handle IDENTIFY, DISCONNECT, etc., as well. 904 */ 905 sc->sc_stat[0] = esp->esp_fifo; 906 sc->sc_msg[0] = reg = esp->esp_fifo; 907 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 908 if (reg == MSG_CMD_COMPLETE) { 909 sc->sc_state = S_FI; 910 return (ACT_CONT); 911 } 912 if (SCSIMSGLEN(reg) != 1) { 913 printf("%s: target %d is naughty\n", 914 sc->sc_dev.dv_xname, sc->sc_targ); 915 return (ACT_RESET); 916 } 917 printf("%s: warning: target %d returned msg 0x%x\n", 918 sc->sc_dev.dv_xname, sc->sc_targ, reg); 919 sc->sc_state = S_FI; 920 return (ACT_CONT); 921 922 case S_MI: 923 if ((reg & ESPINTR_SVC) == 0) { 924 esperror(sc, "missing phase after msg in"); 925 return (ACT_RESET); 926 } 927 reg = ESP_NFIFO(sc->sc_espfflags); 928 for (i = 0; i < reg; i++) 929 sc->sc_msg[i] = esp->esp_fifo; 930 break; 931 932 case S_FI: 933 esperror(sc, "target did not disconnect"); 934 return (ACT_RESET); 935 } 936 937 /* 938 * Things are still moving along. The phase tells us 939 * what the device wants next. Do it. 940 */ 941 switch (sc->sc_espstat & ESPSTAT_PHASE) { 942 943 case ESPPHASE_DATA_OUT: 944 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data out without command"); 945 if (sc->sc_dmactl & DMA_READ) { 946 esperror(sc, "wrong phase (want to read)"); 947 return (ACT_RESET); 948 } 949 newstate = S_DO; 950 goto do_data_xfer; 951 952 case ESPPHASE_DATA_IN: 953 if (!sc->sc_sentcmd) esperror(sc, "DIAG: data in without command"); 954 if (!(sc->sc_dmactl & DMA_READ)) { 955 esperror(sc, "wrong phase (want to write)"); 956 return (ACT_RESET); 957 } 958 newstate = S_DI; 959 do_data_xfer: 960 if (sc->sc_resid == 0) { 961 esperror(sc, "data count error"); 962 return (ACT_RESET); 963 } 964 965 /* 966 * Compute DMA count based on chip limits. 967 * Set DMA address and load transfer count into 968 * ESP via DMA NOP, then set DMA control, and 969 * then we can start the DMA. 970 */ 971 sc->sc_state = newstate; 972 i = min(sc->sc_resid, ESPMAX); 973 i = min(i, DMAMAX(sc->sc_dmaaddr)); 974 sc->sc_dmasize = i; 975 dma->dma_addr = sc->sc_dmaaddr; 976 esp->esp_tch = i >> 8; 977 esp->esp_tcl = i; 978 esp->esp_cmd = ESPCMD_DMA | ESPCMD_NOP; 979 dma->dma_csr = sc->sc_dmactl; 980 sc->sc_dmaactive = 1; 981 esp->esp_cmd = ESPCMD_DMA | ESPCMD_XFER_INFO; 982 return (ACT_IO); 983 984 case ESPPHASE_CMD: 985 /* 986 * Silly thing wants the command again. 987 * Load it into the FIFO and go to SVC state. 988 */ 989 printf("%s: redoing command\n", sc->sc_dev.dv_xname); 990 cdb = sc->sc_curcdb; 991 reg = SCSICMDLEN(cdb->cdb_bytes[0]); 992 for (i = 0; i < reg; i++) 993 esp->esp_fifo = cdb->cdb_bytes[i]; 994 sc->sc_state = S_SVC; 995 esp->esp_cmd = ESPCMD_XFER_INFO; 996 return (ACT_CONT); 997 998 case ESPPHASE_STATUS: 999 sc->sc_state = S_STAT; 1000 esp->esp_cmd = ESPCMD_INIT_COMP; 1001 return (ACT_CONT); 1002 1003 case ESPPHASE_MSG_IN: 1004 printf("%s: accepting (& ignoring) msg from target %d\n", 1005 sc->sc_dev.dv_xname, sc->sc_targ); 1006 sc->sc_state = S_MI; 1007 esp->esp_cmd = ESPCMD_MSG_ACCEPT; 1008 return (ACT_CONT); 1009 1010 default: 1011 esperror(sc, "bad phase"); 1012 return (ACT_RESET); 1013 } 1014 /* NOTREACHED */ 1015 } 1016 1017 /* 1018 * Clear out target state by doing a special TEST UNIT READY. 1019 * Note that this calls espicmd (possibly recursively). 1020 */ 1021 void 1022 espclear(sc, targ) 1023 register struct esp_softc *sc; 1024 register int targ; 1025 { 1026 1027 /* turn off needclear immediately since this calls espicmd() again */ 1028 sc->sc_needclear &= ~(1 << targ); 1029 sc->sc_clearing = 1; 1030 (void) scsi_test_unit_ready(&sc->sc_hba, targ, 0); 1031 sc->sc_clearing = 0; 1032 } 1033 1034 /* 1035 * THIS SHOULD BE ADJUSTABLE 1036 */ 1037 /* name howlong purpose */ 1038 #define SELECT_WAIT 300000 /* wait for select to complete */ 1039 #define CMD_WAIT 100000 /* wait for next phase, generic */ 1040 #define DATA_WAIT 100000 /* time to xfer data in/out */ 1041 1042 /* 1043 * Send an `immediate' command, i.e., poll until the whole thing is done. 1044 * Return the status byte from the device, or -1 if we timed out. We use 1045 * DMA to transfer the data as the fifo only moves one byte at a time. 1046 */ 1047 int 1048 espicmd(hba, targ, cdb, buf, len, rw) 1049 struct hba_softc *hba; 1050 int targ; 1051 struct scsi_cdb *cdb; 1052 caddr_t buf; 1053 int len, rw; 1054 { 1055 register struct esp_softc *sc = (struct esp_softc *)hba; 1056 register volatile struct espreg *esp = sc->sc_esp; 1057 register volatile struct dmareg *dma = sc->sc_dma; 1058 register int r, s, wait; 1059 register struct sq *sq; 1060 1061 /* 1062 * Wait for any ongoing operation to complete. 1063 */ 1064 s = splbio(); 1065 while (sc->sc_state != S_IDLE) { 1066 sc->sc_iwant = 1; 1067 tsleep((caddr_t)&sc->sc_iwant, PRIBIO, "espicmd", 0); 1068 } 1069 sc->sc_hba.hba_busy = 1; 1070 splx(s); 1071 1072 /* 1073 * Clear the target if necessary. 1074 */ 1075 if (sc->sc_needclear & (1 << targ) && !sc->sc_probing) 1076 espclear(sc, targ); 1077 1078 /* 1079 * Set up DMA transfer control (leaving interrupts disabled). 1080 */ 1081 sc->sc_dmactl = rw & B_READ ? DMA_ENA | DMA_READ : DMA_ENA; 1082 sc->sc_dmaaddr = (u_long)buf; 1083 sc->sc_resid = len; 1084 1085 /* 1086 * Disable hardware interrupts and start select sequence, 1087 * then loop, calling espact() after each ``interrupt''. 1088 */ 1089 DMAWAIT(dma); /* ??? */ 1090 dma->dma_csr = 0; 1091 espselect(sc, targ, cdb); 1092 wait = SELECT_WAIT; 1093 for (;;) { 1094 r = dma->dma_csr; 1095 if (!DMA_INTR(r)) { 1096 if (--wait < 0) { 1097 esperror(sc, "timeout"); 1098 goto reset; 1099 } 1100 DELAY(1); 1101 continue; 1102 } 1103 sc->sc_espstat = esp->esp_stat; 1104 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1105 sc->sc_espintr = esp->esp_intr; 1106 sc->sc_espfflags = esp->esp_fflags; 1107 sc->sc_dmacsr = r; 1108 switch (r = espact(sc)) { 1109 1110 case ACT_CONT: 1111 case ACT_QUICKINTR: 1112 wait = CMD_WAIT; 1113 break; 1114 1115 case ACT_IO: 1116 wait = DATA_WAIT; 1117 break; 1118 1119 case ACT_RESET: 1120 goto reset; 1121 1122 case ACT_DONE: 1123 r = sc->sc_stat[0]; 1124 goto done; 1125 1126 case ACT_ERROR: 1127 r = -1; 1128 goto done; 1129 1130 default: 1131 panic("espicmd action"); 1132 } 1133 } 1134 reset: 1135 espreset(sc, RESET_ESPCHIP); /* ??? */ 1136 r = -1; 1137 done: 1138 sc->sc_state = S_IDLE; 1139 s = splbio(); 1140 if (sc->sc_iwant) { 1141 sc->sc_iwant = 0; 1142 wakeup((caddr_t)&sc->sc_iwant); 1143 } else if ((sq = sc->sc_hba.hba_head) != NULL) { 1144 sc->sc_hba.hba_head = sq->sq_forw; 1145 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1146 } else 1147 sc->sc_hba.hba_busy = 0; 1148 splx(s); 1149 return (r); 1150 } 1151 1152 /* 1153 * Dump (write memory, possibly physmem). 1154 * SPARC higher-level dump code always provides virtual addresses, 1155 * so we need not do any I/O mapping here. 1156 */ 1157 int 1158 espdump(hba, targ, cdb, buf, len) 1159 register struct hba_softc *hba; 1160 int targ; 1161 struct scsi_cdb *cdb; 1162 caddr_t buf; 1163 register int len; 1164 { 1165 register struct esp_softc *sc = (struct esp_softc *)hba; 1166 1167 /* 1168 * If we crashed in the middle of a bus transaction... 1169 */ 1170 if (sc->sc_state != S_IDLE) 1171 espreset(sc, RESET_BOTH); /* ??? */ 1172 return (espicmd(hba, targ, cdb, buf, len, B_WRITE)); 1173 } 1174 1175 /* 1176 * Allocate resources (SCSI bus and DVMA space) for the given transfer. 1177 * Must be called at splbio(). 1178 * 1179 * THIS SHOULD RETURN SUCCESS/FAIL INDICATION 1180 */ 1181 void 1182 espstart(self, sq, bp, dgo, dev) 1183 struct device *self; 1184 register struct sq *sq; 1185 struct buf *bp; 1186 scdgo_fn dgo; 1187 struct device *dev; 1188 { 1189 register struct esp_softc *sc = (struct esp_softc *)self; 1190 1191 if (sc->sc_hba.hba_busy == 0) { 1192 /* 1193 * Bus not busy, nothing to do here, just tell 1194 * this target or unit that it has the SCSI bus. 1195 */ 1196 sc->sc_hba.hba_busy = 1; 1197 (*dgo)(dev, &sc->sc_cdbspace); 1198 } else { 1199 /* 1200 * Bus is busy; just enqueue. 1201 */ 1202 sq->sq_dgo = dgo; 1203 sq->sq_dev = dev; 1204 sq->sq_forw = NULL; 1205 if (sc->sc_hba.hba_head == NULL) 1206 sc->sc_hba.hba_head = sq; 1207 else 1208 sc->sc_hba.hba_tail->sq_forw = sq; 1209 sc->sc_hba.hba_tail = sq; 1210 } 1211 } 1212 1213 /* 1214 * Start buffered I/O. 1215 * Return 0 on success, 1 on failure. 1216 */ 1217 int 1218 espgo(self, targ, intr, dev, bp, pad) 1219 struct device *self; 1220 int targ; 1221 scintr_fn intr; 1222 struct device *dev; 1223 register struct buf *bp; 1224 int pad; 1225 { 1226 register struct esp_softc *sc = (struct esp_softc *)self; 1227 1228 if (sc->sc_needclear & (1 << targ)) 1229 espclear(sc, targ); 1230 1231 /* Set up dma control for espact(). */ 1232 sc->sc_dmactl = bp->b_flags & B_READ ? 1233 DMA_ENA | DMA_READ | DMA_IE : DMA_ENA | DMA_IE; 1234 sc->sc_dmaaddr = (u_long)bp->b_un.b_addr; 1235 sc->sc_resid = bp->b_bcount; 1236 1237 /* 1238 * Enable interrupts and start selection. 1239 * The rest is done in espintr() and espact(). 1240 */ 1241 sc->sc_hba.hba_intr = intr; /* remember dev done function */ 1242 sc->sc_hba.hba_intrdev = dev; /* and its first arg */ 1243 sc->sc_dma->dma_csr = DMA_IE; 1244 espselect(sc, targ, &sc->sc_cdbspace); 1245 return (0); 1246 } 1247 1248 /* 1249 * Handle interrupt. Return 1 if taken. 1250 */ 1251 int 1252 espintr(sc0) 1253 void *sc0; 1254 { 1255 register struct esp_softc *sc = (struct esp_softc *)sc0; 1256 register volatile struct espreg *esp = sc->sc_esp; 1257 register volatile struct dmareg *dma = sc->sc_dma; 1258 register int r, wait; 1259 register struct sq *sq; 1260 1261 r = dma->dma_csr; 1262 if (!DMA_INTR(r)) 1263 return (0); /* not ours */ 1264 sc->sc_intrcnt.ev_count++; 1265 1266 again: 1267 sc->sc_espstat = esp->esp_stat; 1268 sc->sc_espstep = esp->esp_step & ESPSTEP_MASK; 1269 sc->sc_espintr = esp->esp_intr; 1270 sc->sc_espfflags = esp->esp_fflags; 1271 sc->sc_dmacsr = r; 1272 1273 if (sc->sc_state == S_IDLE) { 1274 printf("%s: stray interrupt\n", sc->sc_dev.dv_xname); 1275 dma->dma_csr &= ~DMA_IE; /* ??? */ 1276 return (1); 1277 } 1278 switch (r = espact(sc)) { 1279 1280 case ACT_CONT: /* just return */ 1281 case ACT_IO: 1282 break; 1283 1284 case ACT_RESET: /* please reset esp */ 1285 reset: 1286 espreset(sc, RESET_ESPCHIP); /* ??? */ 1287 /* FALLTHROUGH */ 1288 1289 case ACT_DONE: /* this one is done, successfully */ 1290 case ACT_ERROR: /* this one is done due to `severe' error */ 1291 if (!sc->sc_hba.hba_busy) 1292 panic("espintr sq"); 1293 /* 1294 * This transaction is done. Call the driver's intr routine. 1295 * If an immediate command is pending, let it run in front 1296 * of us, otherwise start the next transation. Note that 1297 * the interrupt routine may run its own immediate commands 1298 * (`request sense' for errors, eg) before we get around to 1299 * the process waiting to do immediate command, but that 1300 * is OK; if we did not set S_IDLE here we could deadlock. 1301 */ 1302 sc->sc_state = S_IDLE; 1303 (*sc->sc_hba.hba_intr)(sc->sc_hba.hba_intrdev, 1304 r == ACT_DONE ? sc->sc_stat[0] : -1, sc->sc_resid); 1305 if (sc->sc_iwant) { 1306 wakeup((caddr_t)&sc->sc_iwant); 1307 sc->sc_iwant = 0; 1308 } else if ((sq = sc->sc_hba.hba_head) != NULL) { 1309 sc->sc_hba.hba_head = sq->sq_forw; 1310 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1311 } else 1312 sc->sc_hba.hba_busy = 0; 1313 break; 1314 1315 case ACT_QUICKINTR: /* wait a short while for another interrupt */ 1316 printf("%s: quickintr: ", sc->sc_dev.dv_xname); 1317 wait = 100; 1318 do { 1319 r = dma->dma_csr; 1320 if (DMA_INTR(r)) { 1321 printf("got one, wait=%d\n", wait); 1322 goto again; 1323 } 1324 } while (--wait > 0); 1325 printf("did not get one\n"); 1326 break; 1327 1328 default: 1329 panic("espintr action"); 1330 } 1331 return (1); 1332 } 1333 1334 /* 1335 * Target or unit decided to let go of the bus early. 1336 */ 1337 void 1338 esprel(self) 1339 struct device *self; 1340 { 1341 register struct esp_softc *sc = (struct esp_softc *)self; 1342 register struct sq *sq; 1343 1344 /* if there is someone else waiting, give them a crack at it */ 1345 if ((sq = sc->sc_hba.hba_head) != NULL) 1346 (*sq->sq_dgo)(sq->sq_dev, &sc->sc_cdbspace); 1347 else 1348 sc->sc_hba.hba_busy = 0; 1349 } 1350